3.7.2.2 Internal Hardware for Antenna Tuning

As shown in the preceding figure, the hardware used for automatic antenna tuning consists of a digitally controlled internal tuning capacitance C_TUNE and an RF amplitude measurement unit, with both connected to pin 5/ANT_TUNE. This pin must be left open if antenna tuning is not used. The following figure shows the internal hardware in more detail, indicating the associated control bits located in the RF front-end registers.

The C_TUNE capacitor has a nominal capacitance range from 4 pF to 9 pF with ±15% tolerance. Its value is controlled by the RF front-end register FEAT.ANTN[3:0] (see Table 3-51). The ANT_TUNE pin is internally biased to VS_PA with a 125 kΩ resistor. The biasing of the C_TUNE capacitor must be enabled with FEEN2.CPBIA and the capacitor value must be set by FEAT.ANTN[3:0]. The capacitor C_TUNE is designed for RF amplitudes below 3V peak (see parameter no 12.30 in RF Transmit Characteristics).

The preceding figure also shows the realization of the amplitude measurement. It consists of an amplitude detector, which can convert the RF amplitude into DC voltage, a DAC and a comparator. The amplitude detector is automatically adjusted by the hardware state-machine and the resulting value is stored in the RF front-end register FEALR.RNGE[1:0]. During automatic antenna tuning, the DAC converts the FEANT.LVLC[3:0] register setting into DC voltage and a comparator is available to decide whether the RF amplitude is higher or lower than the comparison amplitude set by FEALR.RNGE[1:0] and FEANT.LVLC[3:0]. The result of the comparison is read from FESR.ANTS.

The amplitude detector, the DAC and the comparator are only active during automatic tuning, which is enabled with FEEN1.ATEN = 1 and switched off with FEEN1.ATEN = 0.