29.16.1 OCDR – On-chip Debug Register

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.

Name: OCDR
Offset: 0x51
Reset: 0x20
Property: When addressing as I/O Register: address offset is 0x31

Bit 76543210 
 IDRD/OCDR7OCDR 6OCDR 5OCDR 4OCDR 3OCDR 2OCDR 1OCDR 0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – IDRD/OCDR7 USART Receive Complete

The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed.

  • Bit 7 is MSB
  • Bit 1 is LSB

Refer to the debugger documentation for further information on how to use this register.

Bits 0, 1, 2, 3, 4, 5, 6 – OCDR  On-chip Debug Register