25.6.10 Synchronization

Due to asynchronicity between the main clock domain (CLK_EIC_APB) and the peripheral clock domains (GCLK_EIC and CLK_ULP32K), some registers need to be synchronized when written or read.

The following bits are synchronized when written:

• The Software Reset bit in the Control register (CTRLA.SWRST)
• The Enable bit in the Control register (CTRLA.ENABLE)

Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.