37.6.2.1 Initialization

The BIAS and LINEARITY calibration values from the production test must be loaded from the NVM Software Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.

The ADC bus clock (CLK_APB_ADCx) is required to access the related ADC registers. This clock can be enabled in the MCLK - Main Clock Module.

The generic clock (GCLK_ADCx) is required to clock the related ADC. This clock must be configured and enabled in the GCLK - Generic Clock Module before using the ADC.

The following registers are enable-protected, that is, they can only be written when the ADC is disabled (CTRLA.ENABLE = 0):

• The Control B register (CTRLB)
• The Reference Control register (REFCTRL)
• The Event Control register (EVCTRL)
• The Calibration register (CALIB)

Enable-protection is denoted by the "Enable-Protected" property in the register description.