16.7.6 32.768 kHz External Crystal Oscillator (XOSC32K) Control
| Name: | XOSC32K |
| Offset: | 0x14 |
| Reset: | 0x0080 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WRTLOCK | STARTUP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | RUNSTDBY | EN1K | EN32K | XTALEN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 |
Bit 12 – WRTLOCK Write Lock
This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.
| Value | Description |
|---|---|
| 0 | The XOSC32K configuration is not locked. |
| 1 | The XOSC32K configuration is locked. |
Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time
This bit field configures the time after which the XOSC32K clock will be propagated in the design. In order to let a stable clock propagate in the design, the right STARTUP time should be configured after considering the external crystal characteristics and the information provided in the XOSC32K Electrical Specifications section of the Electrical Characteristics chapter. The actual startup time is the number of selected OSCULP32K cycles + 3 XOSC32K cycles.
| STARTUP[2:0] | Number of OSCULP32K Clock Cycles | Number of XOSC32K Clock Cycles | Approximate Equivalent Time [s] |
|---|---|---|---|
| 0x0 | 1 | 3 | 122 µs |
| 0x1 | 32 | 3 | 1.06 ms |
| 0x2 | 2048 | 3 | 62.6 ms |
| 0x3 | 4096 | 3 | 125 ms |
| 0x4 | 16384 | 3 | 500 ms |
| 0x5 | 32768 | 3 | 1 s |
| 0x6 | 65536 | 3 | 2 s |
| 0x7 | 131072 | 3 | 4 s |
Bit 7 – ONDEMAND On Demand Control
This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details, refer to XOSC32K Sleep Behavior.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the XOSC32K behaves during standby sleep mode. For details, refer to XOSC32K Sleep Behavior.
Bit 4 – EN1K 1.024 kHz Output Enable
| Value | Description |
|---|---|
| 0 | The 1.024 kHz output is disabled. |
| 1 | The 1.024 kHz output is enabled, and available internally only for RTC. |
Bit 3 – EN32K 32.768 kHz Output Enable
| Value | Description |
|---|---|
| 0 | The 32.768 kHz output is disabled. |
| 1 | The 32.768 kHz output is enabled, and can be routed to GCLK/GCLK_IO. |
Bit 2 – XTALEN Crystal Oscillator Enable
| Value | Description |
|---|---|
| 0 | External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. |
| 1 | Crystal connected to XIN32/XOUT32. |
Bit 1 – ENABLE Oscillator Enable
| Value | Description |
|---|---|
| 0 | The oscillator is disabled. |
| 1 | The oscillator is enabled. |