12.6 Register Summary

Refer to the Registers Description section for more details on register properties and access permissions.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	WRCTRL	31:24
		23:16	KEY[7:0]
		15:8	PERID[15:8]
		7:0	PERID[7:0]
0x04	EVCTRL	7:0								ERREO
0x05 ... 0x07	Reserved
0x08	INTENCLR	7:0								ERR
0x09	INTENSET	7:0								ERR
0x0A ... 0x0F	Reserved
0x10	INTFLAGAHB	31:24
		23:16
		15:8							HMCRAMCHS_ICM	APBD
		7:0	DIVAS	LPRAMDMAC	APBC	APBA	APBB	HSRAMDSU	HSRAMCM0P	FLASH
0x14	INTFLAGA	31:24
		23:16
		15:8				MCRAMC	FREQM	EIC	RTC	WDT
		7:0	GCLK	SUPC	OSC32KCTRL	OSCCTRL	RSTC	MCLK	PM	PAC
0x18	INTFLAGB	31:24
		23:16
		15:8
		7:0			HMATRIXHS	MTB	DMAC	NVMCTRL	DSU	PORT
0x1C	INTFLAGC	31:24					SMBIST	PDEC	ICM
		23:16		CCL	PTC	DAC	AC	ADC1	ADC0	TC4
		15:8	TC3	TC2	TC1	TC0	TCC2	TCC1	TCC0	CAN1
		7:0	CAN0	SERCOM5	SERCOM4	SERCOM3	SERCOM2	SERCOM1	SERCOM0	EVSYS
0x20	INTFLAGD	31:24
		23:16
		15:8
		7:0				TC7	TC6	TC5	SERCOM7	SERCOM6
0x24 ... 0x33	Reserved
0x34	STATUSA	31:24
		23:16
		15:8				MCRAMC	FREQM	EIC	RTC	WDT
		7:0	GCLK	SUPC	OSC32KCTRL	OSCCTRL	RSTC	MCLK	PM	PAC
0x38	STATUSB	31:24
		23:16
		15:8
		7:0			HMATRIXHS	MTB	DMAC	NVMCTRL	DSU	PORT
0x3C	STATUSC	31:24					SMBIST	PDEC	ICM
		23:16		CCL	PTC	DAC	AC	ADC1	ADC0	TC4
		15:8	TC3	TC2	TC1	TC0	TCC2	TCC1	TCC0	CAN1
		7:0	CAN0	SERCOM5	SERCOM4	SERCOM3	SERCOM2	SERCOM1	SERCOM0	EVSYS
0x40	STATUSD	31:24
		23:16
		15:8
		7:0				TC7	TC6	TC5	SERCOM7	SERCOM6

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