27.7 Register Summary

Refer to the Registers Description section for more details on register properties and access permissions.

The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing between groups. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.


Offset	Name	Bit Pos.	7	6	4	3	2	1	0
0x00	DIR	31:24	DIR[31:24]
		23:16	DIR[23:16]
		15:8	DIR[15:8]
		7:0	DIR[7:0]
0x04	DIRCLR	31:24	DIRCLR[31:24]
		23:16	DIRCLR[23:16]
		15:8	DIRCLR[15:8]
		7:0	DIRCLR[7:0]
0x08	DIRSET	31:24	DIRSET[31:24]
		23:16	DIRSET[23:16]
		15:8	DIRSET[15:8]
		7:0	DIRSET[7:0]
0x0C	DIRTGL	31:24	DIRTGL[31:24]
		23:16	DIRTGL[23:16]
		15:8	DIRTGL[15:8]
		7:0	DIRTGL[7:0]
0x10	OUT	31:24	OUT[31:24]
		23:16	OUT[23:16]
		15:8	OUT[15:8]
		7:0	OUT[7:0]
0x14	OUTCLR	31:24	OUTCLR[31:24]
		23:16	OUTCLR[23:16]
		15:8	OUTCLR[15:8]
		7:0	OUTCLR[7:0]
0x18	OUTSET	31:24	OUTSET[31:24]
		23:16	OUTSET[23:16]
		15:8	OUTSET[15:8]
		7:0	OUTSET[7:0]
0x1C	OUTTGL	31:24	OUTTGL[31:24]
		23:16	OUTTGL[23:16]
		15:8	OUTTGL[15:8]
		7:0	OUTTGL[7:0]
0x20	IN	31:24	IN[31:24]
		23:16	IN[23:16]
		15:8	IN[15:8]
		7:0	IN[7:0]
0x24	CTRL	31:24	SAMPLING[31:24]
		23:16	SAMPLING[23:16]
		15:8	SAMPLING[15:8]
		7:0	SAMPLING[7:0]
0x28	WRCONFIG	31:24	HWSEL	WRPINCFG	WRPMUX	PMUX[3:0]
		23:16		DRVSTR			PULLEN	INEN	PMUXEN
		15:8	PINMASK[15:8]
		7:0	PINMASK[7:0]
0x2C	EVCTRL	31:24	PORTEI3	EVACT3[1:0]	PID3[4:0]
		23:16	PORTEI2	EVACT2[1:0]	PID2[4:0]
		15:8	PORTEI1	EVACT1[1:0]	PID1[4:0]
		7:0	PORTEI0	EVACT0[1:0]	PID0[4:0]
0x30	PMUX0	7:0	PMUXO[3:0]			PMUXE[3:0]
...
0x3F	PMUX15	7:0	PMUXO[3:0]			PMUXE[3:0]
0x40	PINCFG0	7:0		DRVSTR			PULLEN	INEN	PMUXEN
...
0x5F	PINCFG31	7:0		DRVSTR			PULLEN	INEN	PMUXEN