21.6 Register Summary
Refer to the Registers Description section for more details on register properties and access permissions.
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | DLZ | SIGNED | ||||||
0x01 ... 0x03 | Reserved | |||||||||
| 0x04 | STATUS | 7:0 | DBZ | BUSY | ||||||
0x05 ... 0x07 | Reserved | |||||||||
| 0x08 | DIVIDEND | 31:24 | DIVIDEND[31:24] | |||||||
| 23:16 | DIVIDEND[23:16] | |||||||||
| 15:8 | DIVIDEND[15:8] | |||||||||
| 7:0 | DIVIDEND[7:0] | |||||||||
| 0x0C | DIVISOR | 31:24 | DIVISOR[31:24] | |||||||
| 23:16 | DIVISOR[23:16] | |||||||||
| 15:8 | DIVISOR[15:8] | |||||||||
| 7:0 | DIVISOR[7:0] | |||||||||
| 0x10 | RESULT | 31:24 | RESULT[31:24] | |||||||
| 23:16 | RESULT[23:16] | |||||||||
| 15:8 | RESULT[15:8] | |||||||||
| 7:0 | RESULT[7:0] | |||||||||
| 0x14 | REM | 31:24 | REM[31:24] | |||||||
| 23:16 | REM[23:16] | |||||||||
| 15:8 | REM[15:8] | |||||||||
| 7:0 | REM[7:0] | |||||||||
| 0x18 | SQRNUM | 31:24 | SQRNUM[31:24] | |||||||
| 23:16 | SQRNUM[23:16] | |||||||||
| 15:8 | SQRNUM[15:8] | |||||||||
| 7:0 | SQRNUM[7:0] | |||||||||