22.6.1 Control A

Name: CTRLA
Offset: 0x00
Reset: X determined from NVM User Row
Property: PAC Write-Protection, Write-Synchronized Bits

Bit 76543210 
 ALWAYSON    WENENABLE  
Access R/WR/WR/W 
Reset xxx 

Bit 7 – ALWAYSON Always-On

This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain enabled until a power-on Reset is received. When this bit is '1', the Control A register (CTRLA), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these registers are not allowed.

Writing a '0' to this bit has no effect.

This bit is loaded from 10.2.1 NVM User Row Mapping at start-up.

Note: This bit is not synchronized.
ValueDescription
0 The WDT is enabled and disabled through the ENABLE bit.
1 The WDT is enabled and can only be disabled by a Power-on Reset (POR).

Bit 2 – WEN Watchdog Timer Window Mode Enable

This bit enables Window mode. It can only be written if the peripheral is disabled unless CTRLA.ALWAYSON=1.

This bit is loaded from 10.2.1 NVM User Row Mapping at startup.

Note: This bit is not synchronized.
ValueDescription
0 Window mode is disabled (normal operation).
1 Window mode is enabled.

Bit 1 – ENABLE Enable

This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON=0.

This bit is not Enable-Protected.

This bit is loaded from 10.2.1 NVM User Row Mapping at startup.

Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
ValueDescription
0 The WDT is disabled.
1 The WDT is enabled.