21.5.4.1 Initialization

The DIVAS bus clock (CLK_DIVAS_AHB) is required to clock the DIVAS. This clock must be enabled in MCLK - Main Clock Module before using the DIVAS.

The DIVAS configuration cannot be modified while a divide operation is ongoing. The following bits must be written prior to starting a division:

• The Sign Selection bit in the Control A register (CTRLA21.6.1 Control A.SIGNED)
• The Leading Zero Mode bit in the Control A register (CTRLA21.6.1 Control A.DLZ)