4.3 Interrupt Sources

The OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification requires that the interrupt is asserted on the following conditions if the conditions were not already reported in the most recent data footer:
  • Receive data available
  • Transmit buffer space available
  • Extended status bit set

The specification then requires that the SPI controller initiate a data block transaction in order to obtain the current receive data block footer and determine the reason for the interrupt. See the section MAC Frame Receive Data Block Footer for more details on the footer. If the extended status (EXST) bit of the footer is set, the controller should then read the OA_STATUS0 register and, if needed, the OA_STATUS1 register to determine which status bit or bits are set.

The Open Alliance specification defines the operation of these registers. The OA_STATUS0 contains interrupt bits that are defined by the standard, and the SPI host can select which of these bits will cause the extended status bit to be set by modifying the OA_IMASK0 register.

The OA_STATUS1 register contains vendor specific sources; its mask register is OA_IMASK1. This register contains the following bits that can trigger the extended status bit to be set and, if needed an interrupt.
  • SEV - This bit is asserted when bits in the Synchronization Event Status (SEVSTS) register are set. Details are available in the Synchronization Support section.
  • TTSCMA/B/C - These bits are asserted when the SPI host requested that a timestamp be captured when a packet is transmitted, but the transmit timestamp capture was not triggered.
  • TTSCOFA/B/C - These bits are asserted when a timestamp was captured for a transmit packet as requested by the SPI host, but the previously captured transmit timestamp had not been read from the associated transmit timestamp capture register. The previously captured transmit timestamp was therefore overwritten and lost.
  • UV18 - This bit is asserted when an 1.8V supply under voltage condition is detected. Details are available in the Under Voltage Detection (1.8V Supply) section.
  • ECC - This bit is asserted when an SRAM ECC error has been detected. Details are available in the SRAM Error Correction Code (ECC) section.
  • BUSER - This bit is asserted when an internal bus error status has been detected. This may be due to an SRAM error or internal bus parity error. Details are in the SRAM Error Correction Code (ECC) and Bus Parity sections.
  • FSMSTER - This bit is asserted when an internal state machine has been detected making an invalid transition or transitioning into an invalid state. Details are available in the Internal Fault Detection section.
  • TXNER, RXNER - These bits are asserted when an non-recoverable transmit or receive error has occurred. Details are available in the Internal Fault Detection section.