11.1.6 Status 0 Register


Bit	31	30	29	28	27	26	25	24

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
				CPDE	TXFCSE	TTSCAC	TTSCAB	TTSCAA
Access	RO	RO	RO	R/W1C	R/W1C	R/W1C	R/W1C	R/W1C
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PHYINT	RESETC	HDRE	LOFE	RXBOE	TXBUE	TXBOE	TXPE
Access	RO	R/W1C	R/W1C	R/W1C	R/W1C	R/W1C	R/W1C	R/W1C
Reset	0	0	0	0	0	0	0	0

Bit 12 – CPDE Control Data Protection Error

When control register data protection is enabled (see PROTE), this bit is set when a bit error has been detected in a control command received from the SPI host.

Value	Description
`0`	A control command data error has not been detected
`1`	A control command data error has been detected

Bit 11 – TXFCSE Transmit Frame Check Sequence Error

When transmit frame check sequence validation is enabled (see TXFCSVE), this bit will be set when the MAC-PHY receives an Ethernet frame from the SPI host with an invalid frame check sequence.

Value	Description
`0`	Transmit frame check sequence error has not been detected
`1`	Transmit frame check sequence error has been detected

Bit 10 – TTSCAC Transmit Timestamp Capture Available C

This bit is set when a frame has been transmitted to the network and a timestamp has been captured in the Transmit Timestamp Capture C (TTSCC) register and is ready for reading.

Value	Description
`0`	Timestamp has not been captured into the Transmit Timestamp Capture C (TTSCC) register
`1`	Timestamp has been captured into the Transmit Timestamp Capture C (TTSCC) register

Bit 9 – TTSCAB Transmit Timestamp Capture Available B

This bit is set when a frame has been transmitted to the network and a timestamp has been captured in the Transmit Timestamp Capture B (TTSCB) register and is ready for reading.

Value	Description
`0`	Timestamp has not been captured into the Transmit Timestamp Capture B (TTSCB) register
`1`	Timestamp has been captured into the Transmit Timestamp Capture B (TTSCB) register

Bit 8 – TTSCAA Transmit Timestamp Capture Available A

This bit is set when a frame has been transmitted to the network and a timestamp has been captured in the Transmit Timestamp Capture A (TTSCA) register and is ready for reading.

Value	Description
`0`	Timestamp has not been captured into the Transmit Timestamp Capture A (TTSCA) register
`1`	Timestamp has been captured into the Transmit Timestamp Capture A (TTSCA) register

Bit 7 – PHYINT PHY Interrupt

This bit is set when the integrated PHY has signaled an interrupt service request. The host must read the PHY status registers to determine the source of the PHY interrupt.

Note: This bit is cleared by clearing the underlying PHY interrupt source(s).

Value	Description
`0`	PHY interrupt has not been detected
`1`	PHY interrupt has been detected

Bit 6 – RESETC Reset Complete

This bit is set upon a reset of the device.

Value	Description
`0`	Device has not been reset (normal operation)
`1`	Device has been reset and requires configuration

Bit 5 – HDRE Header Error Status

This bit is set when a header was received which failed the parity check.

Value	Description
`0`	No header error detected
`1`	Header error has occured

Bit 4 – LOFE Loss of Framing Error Status

This bit is set when an early deassertion of CS_N has been detected and the MAC-PHY has lost transaction framing with the host.

Value	Description
`0`	Loss of framing error has not been detected
`1`	Loss of framing error has been detected

Bit 3 – RXBOE Receive Buffer Overflow Error Status

This bit is set when received data from the network has overflowed the internal receive buffer and Ethernet frame data has been lost.

Value	Description
`0`	Receive buffer overflow condition has not been detected
`1`	Receive buffer overflow condition has been detected

Bit 2 – TXBUE Transmit Buffer Underflow Error Status

This bit is set when transmit data from the SPI host has under-flowed the internal transmit buffer while the MAC was transmitting the Ethernet frame data to the network in transmit cut-through operation.

Value	Description
`0`	Transmit buffer underflow condition has not been detected
`1`	Transmit buffer underflow condition has been detected

Bit 1 – TXBOE Transmit Buffer Overflow Error Status

This bit is set when transmit Ethernet frame data from the SPI host has over-flowed the internal transmit buffers.

Value	Description
`0`	Transmit buffer overflow condition has not been detected
`1`	Transmit buffer overflow condition has been detected

Bit 0 – TXPE Transmit Protocol Error Status

This bit is set when a transmit data protocol error has been detected.

Value	Description
`0`	Transmit protocol error has not been detected
`1`	Transmit protocol error has been detected

Name:	OA_STATUS0
Address:	0x008

LAN8650/1