11.1.9 Interrupt Mask 0 Register

Name: OA_IMASK0
Address: 0x00C

Bit 3130292827262524 
  
Access RORORORORORORORO 
Reset 00000000 
Bit 2322212019181716 
  
Access RORORORORORORORO 
Reset 00000000 
Bit 15141312111098 
 CPDEMTXFCSEMTTSCACMTTSCABMTTSCAAM 
Access ROROROR/WR/WR/WR/WR/W 
Reset 00111111 
Bit 76543210 
 PHYINTMRESETCMHDREMLOFEMRXBOEMTXBUEMTXBOEMTXPEM 
Access R/WROR/WR/WR/WR/WR/WR/W 
Reset 10111111 

Bit 12 – CPDEM Control Data Protection Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Control Data Protection Error (CPDE) status bit is set in the Status 0 register.
ValueDescription
0 Control data protection error status interrupt enabled
1 Control data protection error status interrupt disabled

Bit 11 – TXFCSEM Transmit Frame Check Sequence Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Frame Check Sequence Error (TXFCSE) status bit is set in the Status 0 register.
ValueDescription
0 Transmit frame check sequence error status interrupt enabled
1 Transmit frame check sequence error status interrupt disabled

Bit 10 – TTSCACM Transmit Timestamp Capture Available C Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Available C (TTSCAC) status bit is set in the Status 0 register.
ValueDescription
0 Transmit timestamp capture available C status interrupt enabled
1 Transmit timestamp capture available C status interrupt disabled

Bit 9 – TTSCABM Transmit Timestamp Capture Available B Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Available B (TTSCAB) status bit is set in the Status 0 register.
ValueDescription
0 Transmit timestamp capture available B status interrupt enabled
1 Transmit timestamp capture available B status interrupt disabled

Bit 8 – TTSCAAM Transmit Timestamp Capture Available A Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Available A (TTSCAA) status bit is set in the Status 0 register.
ValueDescription
0 Transmit timestamp capture available A status interrupt enabled
1 Transmit timestamp capture available A status interrupt disabled

Bit 7 – PHYINTM PHY Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the PHY Interrupt (PHYINT) status bit is set in the Status 0 register.
ValueDescription
0 PHY status interrupt enabled
1 PHY status interrupt disabled

Bit 6 – RESETCM Reset Complete Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Reset Complete (RESETC) status bit is set in the Status 0 register.
Note: The Reset Complete interrupt cannot be disabled. A Reset will always cause the IRQ_N pin to be asserted upon setting of the Reset Complete (RESETC) status bit in the Status 0 register.
ValueDescription
0 Reset complete status interrupt enabled
1 Invalid state (cannot be written)

Bit 5 – HDREM Header Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Header Error (HDRE) status bit is set in the Status 0 register.
ValueDescription
0 Header error status interrupt enabled
1 Header error status interrupt disabled

Bit 4 – LOFEM Loss of Framing Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Loss of Framing Error (LOFE) status bit is set in the Status 0 register.
ValueDescription
0 Loss of framing error status interrupt enabled
1 Loss of framing error status interrupt disabled

Bit 3 – RXBOEM Receive Buffer Overflow Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Receive Buffer Overflow Error (RXBOE) status bit is set in the Status 0 register.
ValueDescription
0 Receive buffer overflow status interrupt enabled
1 Receive buffer overflow status interrupt disabled

Bit 2 – TXBUEM Transmit Buffer Underflow Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Buffer Underflow Error (TXBUE) status bit is set in the Status 0 register.
ValueDescription
0 Transmit buffer underflow status interrupt enabled
1 Transmit buffer underflow status interrupt disabled

Bit 1 – TXBOEM Transmit Buffer Overflow Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Buffer Overflow Error (TXBOE) status bit is set in the Status 0 register.
ValueDescription
0 Transmit buffer overflow status interrupt enabled
1 Transmit buffer overflow status interrupt disabled

Bit 0 – TXPEM Transmit Protocol Error Interrupt Mask

When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Protocol Error (TXPE) status bit is set in the Status 0 register.
ValueDescription
0 Transmit protocol error status interrupt enabled
1 Transmit protocol error status interrupt disabled