11.1.10 Interrupt Mask 1 Register
| Name: | OA_IMASK1 |
| Address: | 0x00D |
This register contains vendor specific status interrupt masks.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SEVM | TTSCMCM | TTSCMBM | TTSCMAM | ||||||
| Access | RO | RO | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TTSCOFCM | TTSCOFBM | TTSCOFAM | BUSERM | UV18M | ECCM | FSMSTERM | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | RO | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXNERM | RXNERM | ||||||||
| Access | RO | RO | RO | RO | RO | RO | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
Bit 28 – SEVM Synchronization Event Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Synchronization Event status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Synchronization event interrupt enabled |
1 |
Synchronization event interrupt disabled |
Bit 26 – TTSCMCM Transmit Timestamp Capture Missed C Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Missed C (TTSCMC) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit Timestamp Capture Missed C interrupt enabled |
1 |
Transmit Timestamp Capture Missed C interrupt disabled |
Bit 25 – TTSCMBM Transmit Timestamp Capture Missed B Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Missed B (TTSCMB) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit Timestamp Capture Missed B interrupt enabled |
1 |
Transmit Timestamp Capture Missed B interrupt disabled |
Bit 24 – TTSCMAM Transmit Timestamp Capture Missed A Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Missed A (TTSCMA) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit Timestamp Capture Missed A interrupt enabled |
1 |
Transmit Timestamp Capture Missed A interrupt disabled |
Bit 23 – TTSCOFCM Transmit Timestamp Capture Overflow C Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Overflow C (TTSCMC) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit Timestamp Capture Overflow C interrupt enabled |
1 |
Transmit Timestamp Capture Overflow C interrupt disabled |
Bit 22 – TTSCOFBM Transmit Timestamp Capture Overflow B Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Overflow B (TTSCMB) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit Timestamp Capture Overflow B interrupt enabled |
1 |
Transmit Timestamp Capture Overflow B interrupt disabled |
Bit 21 – TTSCOFAM Transmit Timestamp Capture Overflow A Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Timestamp Capture Overflow A (TTSCMA) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit Timestamp Capture Overflow A interrupt enabled |
1 |
Transmit Timestamp Capture Overflow A interrupt disabled |
Bit 20 – BUSERM Internal Bus Error Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the internal Bus Error (BUSER) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Internal bus error interrupt enabled |
1 |
Internal bus error interrupt disabled |
Bit 19 – UV18M 1.8V supply Under-Voltage Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the 1.8V supply Under-voltage (UV18) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
1.8V supply under-voltage interrupt enabled |
1 |
1.8V supply under-voltage interrupt disabled |
Bit 18 – ECCM SRAM ECC Error Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the SRAM ECC Error (ECC) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
SRAM ECC error interrupt enabled |
1 |
SRAM ECC error interrupt disabled |
Bit 17 – FSMSTERM FSM State Error Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the FSM State Error (FSMSTER) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
FSM state error interrupt enabled |
1 |
FSM state error interrupt disabled |
Bit 1 – TXNERM Transmit Non-Recoverable Error Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Transmit Non-Recoverable Error (TXNER) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Transmit non-recoverable error interrupt enabled |
1 |
Transmit non-recoverable error interrupt disabled |
Bit 0 – RXNERM Receive Non-Recoverable Error Interrupt Mask
When clear, this bit will enable the assertion of the IRQ_N pin when the Receive Non-Recoverable Error (RXNER) status bit is set in the Status 1 register.
| Value | Description |
|---|---|
0 |
Receive non-recoverable error interrupt enabled |
1 |
Receive non-recoverable error interrupt disabled |