11.1.7 Status 1 Register
| Name: | OA_STATUS1 |
| Address: | 0x009 |
This register contains vendor specific status.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SEV | TTSCMC | TTSCMB | TTSCMA | ||||||
| Access | RO | RO | RO | RO | RO | R/W1C | R/W1C | R/W1C | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TTSCOFC | TTSCOFB | TTSCOFA | BUSER | UV18 | ECC | FSMSTER | |||
| Access | R/W1C | R/W1C | R/W1C | R/W1C | R/W1C | R/W1C | R/W1C | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXNER | RXNER | ||||||||
| Access | RO | RO | RO | RO | RO | RO | R/W1C | R/W1C | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 28 – SEV Synchronization Event
This bit is set when any of the bits within the Synchronization Event Status (SEVSTS) register are set and the associated bit is not disabled in the Synchronization Event Interrupt Mask (SEVIM) regsiter.
| Value | Description |
|---|---|
0 | At least one enabled bit is set in the SEVSTS register |
1 | No enabled bits are set in the SEVSTS register |
Bit 26 – TTSCMC Transmit Timestamp Capture Missed C
This bit is set when a requested timestamp was requested for a transmit frame into Transmit Timestamp Capture C (TTSCC), however, the transmit event was missed. This may be due to failing the transmit packet pattern match, if enabled.
| Value | Description |
|---|---|
0 | No error. |
1 | Requested frame timestamp capture C was missed |
Bit 25 – TTSCMB Transmit Timestamp Capture Missed B
This bit is set when a requested timestamp was requested for a transmit frame into Transmit Timestamp Capture B (TTSCB), however, the transmit event was missed. This may be due to failing the transmit packet pattern match, if enabled.
| Value | Description |
|---|---|
0 | No error. |
1 | Requested frame timestamp capture B was missed |
Bit 24 – TTSCMA Transmit Timestamp Capture Missed A
This bit is set when a requested timestamp was requested for a transmit frame into Transmit Timestamp Capture A (TTSCA), however, the transmit event was missed. This may be due to failing the transmit packet pattern match, if enabled.
| Value | Description |
|---|---|
0 | No error. |
1 | Requested frame timestamp capture A was missed |
Bit 23 – TTSCOFC Transmit Timestamp Capture Overflow C
This bit is set when a requested timestamp was requested for a transmit frame into Transmit Timestamp Capture C (TTSCC), however, the previous captured timestamp stored in TTSCC has not been read yet. The timestamp stored in TTSCC is not overwritten, and the new transmit packet timestamp will not be captured.
| Value | Description |
|---|---|
0 | No error. |
1 | Requested frame timestamp capture C overflowed |
Bit 22 – TTSCOFB Transmit Timestamp Capture Overflow B
This bit is set when a requested timestamp was requested for a transmit frame into Transmit Timestamp Capture B (TTSCB), however, the previous captured timestamp stored in TTSCB has not been read yet. The timestamp stored in TTSCB is not overwritten, and the new transmit packet timestamp will not be captured.
| Value | Description |
|---|---|
0 | No error. |
1 | Requested frame timestamp capture B overflowed |
Bit 21 – TTSCOFA Transmit Timestamp Capture Overflow A
This bit is set when a requested timestamp was requested for a transmit frame into Transmit Timestamp Capture A (TTSCA), however, the previous captured timestamp stored in TTSCA has not been read yet. The timestamp stored in TTSCA is not overwritten, and the new transmit packet timestamp will not be captured.
| Value | Description |
|---|---|
0 | No error. |
1 | Requested frame timestamp capture A overflowed |
Bit 20 – BUSER Internal Bus Error
This bit is set when an internal bus error has been detected. This may occur due to a bus parity error or uncorrectable SRAM error. When this error occurs, the host controller must perform a hardware or software reset of the device.
| Value | Description |
|---|---|
0 | No internal bus error detected |
1 | Internal bus error detected |
Bit 19 – UV18 1.8V supply Under-Voltage Status
Set when an under-voltage condition has been detected on the 1.8V supply.
| Value | Description |
|---|---|
0 | 1.8V supply under-voltage condition has not been detected |
1 | 1.8V supply under-voltage condition has occurred |
Bit 18 – ECC SRAM ECC Error Status
Set when an SRAM ECC error has been detected.
| Value | Description |
|---|---|
0 | No SRAM ECC error detected |
1 | An SRAM ECC error has occurred |
Bit 17 – FSMSTER FSM State Error Status
This bit is set when an internal state machine error has been detected. This may occur due to a random failure that causes a state machine to transition into an unexpected or invalid state. When this error occurs, the host controller must perform a hardware or software reset of the device.
| Value | Description |
|---|---|
0 | No internal state machine errors detected |
1 | Internal state machine error has occurred |
Bit 1 – TXNER Transmit Non-Recoverable Error Status
This bit is set when an internal non-recoverable transmit error has been detected. When this error occurs, the host controller must perform a hardware or software reset of the device.
| Value | Description |
|---|---|
0 | No transmit non-recoverable errors |
1 | Transmit non-recoverable error has occurred |
Bit 0 – RXNER Receive Non-Recoverable Error Status
This bit is set when an internal non-recoverable receive error has been detected. When this error occurs, the host controller must perform a hardware or software reset of the device.
| Value | Description |
|---|---|
0 | No receive non-recoverable errors |
1 | Receive non-recoverable error has occurred |