3.5.4 CLC1

Configure CLC1 as shown in Figure 3-5. Select 2-input D flip-flop with R in the Mode field. Select TMR6_OUT as the clock signal to the D Flip-Flop register. Select CLC3_OUT (the output signal of CLC3) and logical AND-it with the default CLCIN0 (the input signal of CLC3) as an input signal to CLC1. Connect the TMR6_OUT signal to the CLC logic gate 1 as highlighted in the red circle shown in Figure 3-5. Connect CLC3_OUT and CLCIN0 to the CLC logic gates 2 and invert both the input and output signals of the CLC logic gates 2 as highlighted in the red circles.