3.5.3 CLC3

Configure CLC3 as shown in Figure 3-4. Select 2-input D flip-flop with R in the Mode field. Select Timer6 overflow signal TMR6_OUT as the clock to the D Flip-Flop register. Select CLCIN0 as the input signal. Connect these two signals to the CLC logic gates 1 and 2 respectively as highlighted in the red circle in Figure 3-4.