30.11.9 External Interrupt Asynchronous Mode

Important: On PIC32CMSG devices where the EIC is configured as Mix-Secure, read and write accesses are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the Non-Secure accesses to an Enabled-Protected register as it will not be possible for the Non-Secure to configure it once this register is enabled by the Secure application. This will require some veneers to be implemented on Secure side.

Table 30-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	ASYNCH
Offset:	0x18
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	ASYNCH[31:24]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ASYNCH[23:16]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ASYNCH[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ASYNCH[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – ASYNCH[31:0] Asynchronous Edge Detection Mode

The bit x of ASYNCH set the Asynchronous Edge Detection mode for the interrupt associated with the EIC_EXTINTx pins.

Value	Name	Description
0	SYNC	EIC_EXTINTx edge detection is synchronously operated
1	ASYNC	EIC_EXTINTx edge detection is asynchronously operated