30.11.2 Non-Maskable Interrupt Control
Important: On PIC32CMSG devices where the EIC is configured as Mix-Secure,
read and write accesses are allowed only if the NMI interrupt is set as Non-Secure
in the NONSEC register (NONSEC.NMI bit).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | NMICTRL |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NMIASYNCH | NMIFILTEN | NMISENSE[2:0] | |||||||
| Access | RW | RW | RW | RW | RW | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 4 – NMIASYNCH Asynchronous Edge Detection Mode
The NMI edge detection can be operated synchronously or asynchronously to the EIC clock.
| Value | Name | Description |
|---|---|---|
| 0 | SYNC | Edge detection is clock synchronously operated |
| 1 | ASYNC | Edge detection is clock asynchronously operated |
Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable
| Value | Description |
|---|---|
| 0 | NMI filter is disabled. |
| 1 | NMI filter is enabled. |
Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense Configuration
These bits define on which edge or level the NMI triggers.
| Value | Name | Description |
|---|---|---|
| 0 | NONE | No detection |
| 1 | RISE | Rising-edge detection |
| 2 | FALL | Falling-edge detection |
| 3 | BOTH | Both-edges detection |
| 4 | HIGH | High-level detection |
| 5 | LOW | Low-level detection |