30.11.13 Pin State

Important: On PIC32CMSG devices where the EIC is configured as Mix-Secure, non-secure read accesses will return the true value only for external interrupt x (EXTINTx) set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Else the read will return 0 for the external interrupt x (EXTINTx) set as Secure in the NONSEC register (NONSEC.EXTINTx bit).

Table 30-14. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PINSTATE
Offset:	0x38
Reset:	0x00000000
Property:	R


Bit	31	30	29	28	27	26	25	24
	PINSTATE[31:24]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PINSTATE[23:16]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PINSTATE[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PINSTATE[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – PINSTATE[31:0] Pin State

These bits return the valid pin state of the debounced external interrupt pin, EIC_EXTINTx.