34.6.4.2.6 Transferring Data

In Host mode (CTRLD.MODE=0x3), when Host Client Enable Select (CTRLB.MSSEN) is ‘1’, hardware will control the SS line.

When Host Client Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line low.

For configurations where the FIFO is disabled or not implemented, when writing a character to the Data register (DATA), the character will be transferred to the Shift register. Once the content of TxDATA has been transferred to the Shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA. If the FIFO is enabled, INTFLAG.DRE will be set when at least FIFO threshold (CTRLC.TXTRHOLD) locations in TX FIFO are empty. Characters can be written as long as the FIFO is not full.

Each time one character is shifted out from the Host, another character will be shifted in from the Client simultaneously. If the receiver is enabled (CTRLE.RXEN=1), the contents of the Shift register will be transferred to the receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in.

For configurations where the FIFO is disabled or not implemented, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. For configuration where the FIFO is enabled, RXC is set when at least RXTRHOLD data are available in the RX FIFO. In both cases, the received data can be retrieved by reading DATA.

For configurations where the FIFO is disabled or not implemented, when the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. For configuration where the FIFO is enabled, TXC is set when the transmit is complete and the TX FIFO is empty. When the transaction is finished, the Host must pull the SS line high to notify the Client. If Host Client Select Enable (CTRLB.MSSEN) is set to '0', the software must pull the SS line high.

In Client mode (CTRLD.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the SS pin is pulled high. Software may update the contents of Tx buffer at any time as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set.

When SS is pulled low and SCK is running, the Client will sample and shift out data according to the Transaction mode set.

For configurations where the FIFO is disabled or not implemented, when the content of DATA has been loaded into the Shift register, INTFLAG.DRE will be set, and new data can be written to DATA. If the FIFO is enabled, INTFLAG.DRE will be set when at least FIFO threshold (CTRLC.TXTRHOLD) locations in TX FIFO are empty. When DATA or FIFO threshold locations are empty respectivly, it takes three CLK_SERCOM_ APB cycles for INTFLAG.DRE to be set.

Similar to the Host, the Client will receive one character for each character transmitted. A character will be transferred into the receive buffer within the same clock cycle its last data bit is received. The received character can be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set. For configurations where the FIFO is disabled or not implemented, the RXC is set when a character reception is complete. If the FIFO is enabled, the RXC is set when at least RX threshold (CTRLC.RXTRHOLD) data are received.

When the Host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set.

After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the Shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by using the preloading feature. Refer to Preloading of the Client Shift Register.

When transmitting several characters in one SPI transaction, the data has to be written into the DATA register with at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously received character will be transmitted.