31.3.3.7 Conversion Timing

Some of the analog modules in the ADC are disabled between conversions and require time to initialize before the conversion starts. Only the modules used by the current ADC configuration are enabled, and since the initializations run in parallel, the limiting factor is the module with the slowest initialization time.

By writing the Low Latency (LOWLAT) bit in the Control A (ADCn.CTRLA) register to ‘1’, the latency of the ADC peripheral can be reduced. This will keep the configured modules continuously enabled, effectively removing all initialization time at the start of a conversion. Initialization time is still needed when enabling the ADC for the first time and reconfiguring the ADC to use an input or reference that requires initialization. The ADC Busy (ADCBUSY) bit in the Status (ADCn.STATUS) register can be used to check if initialization is ongoing.

The following table shows the initialization times required by the different analog modules.

Table 31-5. ADC Initialization Timing
Analog Module	LOWLAT	Initialization Time (µs)
ADC	`0`	10
ADC	`1`⁽¹⁾	0
Settling of internal references	`0`	60
Settling of internal references	`1`⁽¹⁾	2⁽²⁾
Settling of internal references after changing from one internal reference voltage to another	`X`	35
Settling of external reference or VDD as the reference	`X`	2
Settling of internal Temperature Sensor input	`0`	60
Settling of internal Temperature Sensor input	`1`⁽¹⁾	0
Settling of internal Analog Comparator Reference DAC input	`0`	35
Settling of internal Analog Comparator Reference DAC input	`1`⁽¹⁾	0
Selecting VDD/10 as the input	`X`	2

Note:

The LOWLAT timing values are valid between two conversions that both have the LOWLAT bit written to ‘1’.
When changing from one internal reference voltage to another internal reference voltage, the full 60 μs delay will be used if changing from a non-internal reference to an internal reference.

The sampling period of the input to the ADC is configured through the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as SAMPDUR + 1 CLK_ADC cycles.