31.3.3.7.2 Series Accumulation

The figure below illustrates the timing diagram for the ADC when running in Series Accumulation mode.

Figure 31-4. Timing Diagram - Series Accumulation
Note:
  1. The time from when the conversion has finished to when the outputs are available in the registers is 0.5 CLK_ADC cycles followed by one CLK_PER cycle. With a minimum prescaler of two, this sums up to a maximum of one CLK_ADC cycle.
  2. The time from when the final conversion has finished to when the Result (ADCn.RESULT) register is updated is 0.5 CLK_ADC cycles followed by two CLK_PER cycles. With a minimum prescaler of two, this sums up to the maximum of 1.5 CLK_ADC cycles.
  3. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, which eliminates the initialization time when triggering the next conversion.

The number of samples to accumulate is set by the Sample Number (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register.

The total conversion time for each separate sample is calculated as follows:

t c o n v ⁢ = t i n i t i a l i z a t i o n + SAMPDUR + 1 + 10 + 1 f CLK_ADC