31.3.3.7.1 Single Conversion

The figure below illustrates the timing diagram for the ADC when running in Single 8- or 10-bit mode.

Figure 31-3. Timing Diagram - Single Conversion

Note:

In Single 8-bit mode, the length of the Conversion state is eight CLK_ADC cycles. In all other modes, it is ten cycles.
The time from when the conversion has finished to when the outputs are available in the registers is 0.5 CLK_ADC cycles followed by one CLK_PER cycle. With a minimum prescaler of two, this sums up to a maximum of one CLK_ADC cycle.
If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, which eliminates the initialization time when triggering the next conversion.

The total conversion time for a single result is calculated as follows:

t_{c o n v} (10-bit) = t_{i n i t i a l i z a t i o n} + \frac{SAMPDUR + 1 + 10 + 1}{f_{CLK_ADC}}

t_{c o n v} (8-bit) = t_{i n i t i a l i z a t i o n} + \frac{SAMPDUR+ 1 + 8 + 1}{f_{CLK_ADC}}

If the Free-Running (FREERUN) bit is set to ‘1’ in the Control F (ADCn.CTRLF) register, a new conversion will start immediately after a result is available in the Result (ADCn.RESULT) register. The Free-Running conversion rate (f_conv) is calculated as follows:

f_{conv} (10-bit) = \frac{f_{CLK_ADC}}{SAMPDUR+ 1 + 10 + 1}

f_{conv} (8-bit) = \frac{f_{CLK_ADC}}{SAMPDUR+ 1 + 8 + 1}