20.1.5 MCHP Status Value Register
| Name: | MCHP Status Value Register |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPS | NVMERR | CFGRDY | FCBUSY | FAEN | DEVRST | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CPS Code-Protect State bit
| Value | Description |
|---|---|
| 1 | Device is not code-protected |
| 0 | Device is code-protected |
Bit 5 – NVMERR NVMCON Status bit
Note: This bit is not implemented in the
PIC32MX320/340/360/420/440/460 devices.
| Value | Name |
|---|---|
| 1 | An Error occurred during NVM operation |
| 0 | An Error did not occur during NVM operation |
Bit 3 – CFGRDY Code-Protect State bit
| Value | Name |
|---|---|
| 1 | Configuration has been read and CP is valid |
| 0 | Configuration has not been read |
Bit 2 – FCBUSY Flash Controller Busy bit
| Value | Name |
|---|---|
| 1 | Flash controller is busy (erase is in progress) |
| 0 | Flash controller is not busy (either erase has not started or it has finished) |
Bit 1 – FAEN Flash Access Enable bit
Note: This bit is not implemented in the PIC32MK and the
PIC32MZ family devices.
| Value | Name |
|---|---|
| 1 | Flash access is enabled |
| 0 | Flash access is disabled (processor accesses are blocked) |
Bit 0 – DEVRST Device Reset State bit
| Value | Name |
|---|---|
| 1 | Device Reset is active |
| 0 | Device Reset is not active |