AT13053

4.2.7 Pin Change Mask Register 0

Name:	PCMSK0
Offset:	0x0F
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	PCINTn[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – PCINTn[7:0] Pin Change Enable Mask [n = 7:0]

Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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