When the PCIE0 bit
is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change
interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the
PCMSK Register.
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