4.2.1 Digital Input Disable Register 0
| Name: | DIDR0 |
| Offset: | 0x17 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADC3D | ADC2D | ADC1D | ADC0D | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – ADC3D ADC3 Digital Input Disable
Bit 2 – ADC2D ADC2 Digital Input Disable
Bit 1 – ADC1D ADC1 Digital Input Disable
Bit 0 – ADC0D ADC0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
