30.8.4.5 Power Domain Controller


Power Domain State
Sleep Mode	STDBYCFG.RAMCFG	HIBCFG.RAMCFG	PD_CORE_SW	PD_CORE_BU	PD_CORE_RAMx
Active	N/A	N/A	active	active	active
Idle	N/A	N/A	active	active	active
Standby with sleepwalking	N/A	N/A	active	active	active
Standby or LV Standby - case 1 (see Note1)	RET	N/A	active	active	all retained
Standby or LV Standby - case 2 (see Note1)	OFF	N/A	active	active	off
Hibernate or LV Hibernate - case 1 (see Note1)	N/A	RET	off	active	all retained
Hibernate or LV Hibernate - case 2 (see Note1)	N/A	off	off	active	off
Backup	N/A	off	off	active	off
Off	N/A	N/A	off	off	off

Note: Low Voltage option for LV_Standby or LV-Hibernate does not have any effect on this power-domain state table.

The Power Domain Controller provides several ways of how power domains are handled while the device is in Standby, Hibernate, or Backup mode:

Standby mode:

When running a Sleepwalking task, VDDCORE_RAM_PD power domain is active whatever the STDBYCFG.RAMCFG is set to retain all RAM memory.

Hibernate mode:

When entering a Hibernate mode, the VDDCORE_SW_PD power domain is off. As in Standby mode, the VDDCORE_RAM_PD power domain can be selectively turned ON or OFF by using HIBCFG.RAMCFG field.

When entering Backup mode, the VDDCORE_SW_PD and VDDCORE_RAM_PD power domains are off, as well as the dedicated power domain (VDDCORE_USB_PD). VDDCORE_BU_PD is still active (powered by LPVREGC).

When entering Backup mode, the VDDCORE_SW_PD and VDDCORE_RAM_PD power domains are off, as well as the dedicated power domain. VDDCORE_BU_PD is still active (powered by LPVREGC).

OFF mode:

When entering Off mode, all the power domains are off. I/Os are in high-impedance mode except the RESET_N pad which is still in input mode able to detect a reset to wake up the chip.