30.8.4.6 Regulators, RAMs, and NVM State in Sleep Modes

Idle sleep mode:

GCLK clocks, regulators, NVM, and RAM are not affected in Idle Sleep mode and operate normally.

Standby Sleep mode:

By default, in Standby Sleep mode, the RAMs, NVM, and regulators are automatically set in Low-Power mode in order to reduce power consumption. If SUPC.VREGCTRL.LVSTDBY bit is zero, then the output voltage regulator is kept to nominal value (1.2V). If LVSTDBY is enabled, this mode is called LVSTANDBY.

• The RAM can be disabled when STDBYCFG.RAMCFG = 0 when the device is in Standby mode. RAM contents are retained.
• If not powered-down, the RAM can be set in Low-Power mode according to STDBYCFG.LPRAM.
• If neither powered-down nor Low-Power mode is enabled, the RAM data is retained and not set in retention mode. In this case, the wakeup-time is better as there is no need to turn OFF/ON the RAM power-switches.

Non-Volatile Memory:

The NVM is automatically set in Low-Power mode according to Flash panel configuration.

NVM is automatically set in Low-Power mode according to Flash Panel configuration (FCR.CTRLB.SLP[1:0]). Flash can be in configured to enter auto-standby (with fast wakeup) or Fash-hibernate (powered down w/ slow wakeup).

CTRLB.SLP[1:0]: NVM Power Reduction Mode selection during system Standby Sleep.

• 11 = Enter Flash Hibernate on entry to Standby w/ wakeup on first access
• 10 = Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby
• 01 = RSVD
• 00 = Enter Auto Standby on entry to Standby

Regulators: By default, in Standby Sleep mode, the PM analyzes the device activity to set the regulators (for PD_CORE_SW and PD_CORE_RAMx) to either low-power or full-power mode, to supply the VDDCORE_SW and VDDCORE_RAM, according to the SUPC -> VREGCTRL.LVSTDBY bit.

Hibernate Sleep mode:

• The RAM can be powered-down according to the HIBCFG.RAMCFG bit when the device is in Standby mode. If powered-down, the data will be lost (VDDCE and VDDPE are powered-down).
• If not powered-down, the RAM can be set in low-power mode according to the HIBCFG.LPRAM bit. if in low-power mode, the data is retained (RET1N signal is set, VDDPE voltage is powered-down, VDDCE is kept powered).
• If neither powered-down nor low-power mode, the RAM are retained and not set in retention mode (RET1N is inactive and VDDPE/VDDCE are kept powered on). In this case, the wake-up time is better as there is no need to turn off or on the VDDPE/VDDCE power switch.
• Non-Volatile Memory: The NVM is powered-down.
• Regulators: VDDCORE_RAM_PD is on with reduced voltage if SUPC -> VREGCTRL.LVHIB is set. VREGSW is off.
  Note: If the LVHIB bit is ‘0’, then the VREGRAM output voltage is not reduced. On the contrary, if LVHIB is set, this mode is called LV Hibernate Sleep mode.