34.8.8 Channel n Control
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHANNELn |
| Offset: | 0x20 + n*0x08 [n=0..11] |
| Reset: | 0x00008000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – ONDEMAND Generic Clock On Demand
This bit is used to determine whether the generic clock is requested.
This bit has no effect for channels when asynchronous path is selected or for channels with asynchronous support only.
This bit is always read zero for channels with asynchronous support only.
| Value | Description |
|---|---|
| 0 | Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. |
| 1 | Generic clock is requested on demand while an event is handled |
Bit 14 – RUNSTDBY Run in standby
This bit is used to define the behavior during standby sleep mode, for a resynchronized channel.
This bit has no effect for channels when asynchronous path is selected or for channels with asynchronous support only.
This bit is always read zero for channels with asynchronous support only.
| Value | Description |
|---|---|
| 0 | The channel is disabled in standby sleep mode. |
| 1 | The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit. |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| Value | Name | Description |
|---|---|---|
| 0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path |
| 2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path |
| 3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path |
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
| Value | Name | Description |
|---|---|---|
| 0x0 | ASYNCHRONOUS | Asynchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| Other | - | Reserved |
Bits 6:0 – EVGEN[6:0] Event Generator Selection
These bits are used to choose the event generator to connect to the selected channel.
| Value | Event Generator | Description |
|---|---|---|
| 0x01 | SUPC_LVDET | SUPC fail detection |
| 0x02 | OSCCTRL_XOSC_FAIL | XOSC fail detection |
| 0x03 | OSC32KCTRL_XOSC32K_FAIL | XOSC32K fail detection |
| 0x04 | SUPC_BOD33DET | SUPC BOD33 detection |
| 0x06-0x0D | RTC_PERx | RTC period 0-7 |
| 0x0E-0x11 | RTC_CMPx | RTC comparison x=0-3 |
| 0x12 | RTC_TAMPER | RTC tamper detection |
| 0x13 | RTC_OVF | RTC overlow |
| 0x14 | RTC_PERD | RTC |
| 0x15-0x24 | EIC_EXTINTx | EIC external interrupt, x=0-15 |
| 0x25-0x28 | DMAC_CHx | DMAC channel, x=0-3 |
| 0x29 | TC0_OVF | TC0 overflow |
| 0x2A | TC0_TRG | TC0 trigger |
| 0x2B | TC0_CNT | TC0 count |
| 0x2C-2D | TC0_MCx | TC0 match/compare, x=0-1 |
| 0x2E | TC1_OVF | TC1 overflow |
| 0x2F | TC1_TRG | TC1 trigger |
| 0x30 | TC1_CNT | TC1 count |
| 0x31-0x32 | TC1_MCx | TC1 match/compare, x=0-1 |
| 0x33 | TC2_OVF | TC2 overflow |
| 0x34 | TC2_TRG | TC2 trigger |
| 0x35 | TC2_CNT | TC2 count |
| 0x36-0x37 | TC2_MCx | TC2 match/compare |
| 0x38 | TC3_OVF | TC3 overflow |
| 0x39 | TC3_TRG | TC3 trigger |
| 0x3A | TC3_CNT | TC3 count |
| 0x3B-3C | TC3_MCx | TC3 match/compare, x=0-1 |
| 0x3D | TC4_OVF | TC4 overflow |
| 0x3E | TC4_TRG | TC4 trigger |
| 0x3F | TC4_CNT | TC4 count |
| 0x40-0x41 | TC4_MCx | TC4 match/compare, x=0-1 |
| 0x42 | TC5_OVF | TC5 overflow |
| 0x43 | TC5_TRG | TC5 trigger |
| 0x44 | TC5_CNT | TC5 count |
| 0x45-0x46 | TC5_MCx | TC5 match/compare, x=0-1 |
| 0x47 | TC6_OVF | TC6 overflow |
| 0x48 | TC6_TRG | TC6 trigger |
| 0x49 | TC6_CNT | TC6 count |
| 0x4A-0x4B | TC6_MCx | TC6 match/compare, x=0-1 |
| 0x4C | ADC_CHRDY | ADC resolution ready |
| 0x4D | ADC_CMP | ADC window monitor |
| 0x4E-0x4F | AC_COMP | AC comparator |
| 0x50 | AC_WIN0 | AC window |
| 0x51 | PTC_EOC | PTC end of conversion |
| 0x52 | PTC_WCOMP | PTC window comparator |
| 0x53-0x56 | CCL0_LUTOUT | CCL0 output, x=0-3 |
| 0x57-0x5A | CCL1_LUTOUT | CCL1 output, x=0-3 |