Note: Interrupt flags must be cleared and then read back to confirm the clear before
exiting the ISR to avoid double interrupts.
Table 34-19. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
INTFLAG
Offset:
0x1D6
Reset:
0x00
Property:
RW
Bit
7
6
5
4
3
2
1
0
NSCHK
Access
RW
Reset
0
Bit 0 – NSCHK Non-Secure Check
DS60001921A
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