33.2.7.1 Flash Panel ECC Organization
The following table shows the ECC Calculation Vector bit order with respect to flash data bits and parity bits. The first column is the ECC Calculation Vector. The next two columns map the Read/Write Data and ECC Parity bits to the Calculation Vector. V[n] defines the bit which is selected by FFLT*PTR, so n=FFLT*PTR.
| Vector Bits | Data Bits | ECC Parity Bits |
|---|---|---|
| V[n] | D[n] | EP[n] |
| 0 | - | 0 |
| 1 | - | 1 |
| 2 | - | 2 |
| 3 | 0 | - |
| 4 | - | 3 |
| 7:5 | 3:1 | - |
| 8 | - | 4 |
| 15:9 | 10:4 | - |
| 16 | - | 5 |
| 31:17 | 25:11 | - |
| 32 | - | 6 |
| 63:33 | 56:26 | - |
| 64 | - | 7 |
| 71:65 | 63:57 | - |
| 127:72 | 119:63 | - |
| 128 | - | 8 |
| 136:129 | 127:120 | - |
| 255:137 | 246:128 | - |
| 256 | - | 9 |
| 265:257 | 255:247 | - |
The following table shows the ECCCTL and CTL field decode. The CTL field is stored in Flash and the fault logic can inject errors into it based on FFLTCTRL.CTLFLT.