19.6.7 Multi-Processor Support

The DSU can support multiple CPU cores. If there is a single-core, it will be referred to as CPU0. Additional cores will be indexed as CPU1, CPU2, and so on. Each CPU connects a different bus system. The DAP implements one Memory Access Port (MEM-AP) per CPU and allows debug tools to access each CPU’s bus system. Debug tools must select the correct MEM-AP at the debug port level depending on the targeted bus system.

• MEM-AP0 is disabled (by decreasing order of priority) when:
  • STATUSB.APDIS is high
  • CPU0.DAL = 0 and no cold-plugging detected.

Once enabled, MEM-AP0 always has access to the DSU external space to enable communications between the device and external tools.

• MEM-AP1 is disabled when:
  • STATUSB.APDIS is high
  • When STATUSB.DBGPRES = 0
  • when their respective DAL.CPU1 level is not equal to 2.