11.1.8.13 12-bit ADC Characteristics

Table 11-61. ADC Power Supply and Voltage Reference Input Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	3.6	V
I_VDDIN33	Current consumption on VDDIN33⁽¹⁾⁽²⁾	Low speed (f_S ≤ 500 kS/s ADC_ACR.IBCTL = (00)₂)	–	1.0	mA
I_VDDIN33	Current consumption on VDDIN33⁽¹⁾⁽²⁾	Full speed (f_S ≤ 1 MS/s ADC_ACR.IBCTL = (01)₂)	–	1.8	mA
V_ADVREFP	ADVREFP input voltage range	–	2.4	2.55	V
R_ADVREFP	ADVREFP input resistance to ground⁽²⁾	ADC off	7.2	12	kΩ
R_ADVREFP	ADVREFP input resistance to ground⁽²⁾	ADC on	1	–	MΩ
C_ADVREFP	Recommended decoupling capacitor on ADVREFP	–	1	–	μF

Note:

The 12-bit ADC is powered by the VDDOUT25 regulator, which is supplied from VDDIN33.
Simulation data

Table 11-62. ADC Timing Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
f_CKADC	ADC clock frequency	ADC_ACR.IBCTL = (00)₂	0.1	10	MHz
f_CKADC	ADC clock frequency	ADC_ACR.IBCTL = (01)₂	0.2	20	MHz
t_CONV	ADC conversion time⁽¹⁾	–	20	–	t_CKADC
f_S	Sampling rate⁽²⁾	ADC_ACR.IBCTL = (00)₂	–	0.5	MS/s
f_S	Sampling rate⁽²⁾	ADC_ACR.IBCTL = (01)₂	–	1	MS/s
t_START	Start-up time⁽³⁾	From Off to On	–	5	μs
t_TRACK	Track and hold time⁽³⁾⁽⁴⁾	–	300	–	ns

Note:

t_CONV= t_CH + t_TRACK + 14 x t_CKADC with t_CKADC= 1 / f_CKADC. The parameter t_CH = 0 when the ADC operates in the same input mode (single-ended, pseudo-differential or differential) for the current conversion than for the previous one. t_CH = 2 when the ADC input mode is changed to perform the current conversion.
f_S = 1 / t_CONV
Simulation data
See Track and Hold Time versus Source Impedance – Sampling Rate.

Table 11-63. ADC Analog Input Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_FS	Analog input full scale range⁽¹⁾	ADC_CCR.DIFFx = 0	0	V_ADVREFP	V
V_FS	Analog input full scale range⁽¹⁾	ADC_CCR.DIFFx = 1	-V_ADVREFP	V_ADVREFP	V
V_INCM	Common mode input range in Differential Input mode⁽²⁾	ADC_CCR.DIFFx = 1	0.4 x V_DDANA	0.6 x V_DDANA	V
C_S	ADC sampling capacitance⁽³⁾	–	–	3	pF
C_{P_ADx}	ADx input parasitic capacitance⁽³⁾⁽⁴⁾	ADx pin configured as analog input	–	7	pF
R_ON	Internal series resistor⁽³⁾⁽⁴⁾	–	–	2	kΩ
Z_IN	Common mode input impedance⁽³⁾⁽⁵⁾	On ADx pin	1 / (f_S x C_S)	–	Ω
R_CH30	VBAT resistive attenuator impedance⁽³⁾	–	100	140	kΩ
G_CH30	VBAT channel gain⁽³⁾	–	0.594	0.606	–

Note:

V_FS = (V_ADx- V_GNDANA) in Single-ended mode, V_FS = (V_ADx- V_AD11) in Pseudo-differential mode, and V_FS= (V_ADx- V_ADx+1) in Differential mode
V_INCM = (V_ADx + V_ADx+1) / 2
Simulation data
With respect to the equivalent model of the figure Equivalent Model of the Acquisition Path
Assuming conversion on one single channel

Figure 11-46. Acquisition Path Block diagram

For tracking time calculation, during the sampling phase of the converter, this acquisition path can be reduced to the equivalent model of the following figure, where:

R_ON = R_MUX + R_S
C_{P_ADX} = C_PX + C_{P_MUX}

Figure 11-47. Equivalent Model of the Acquisition Path

See Track and Hold Time versus Source Impedance – Sampling Rate for further details on the use of this model.

In the following table, unless otherwise specified, the specifications are provided for two speed operating ranges.

Source resistance = 50 Ω
ADC_EMR.OSR<2:0> = (000)₂
Low-speed
- f_CKADC = 10 MHz, f_S = 500 kS/s
- ADC_ACR.IBCTL = (00)₂

High-speed
- f_CKADC = 20 MHz, f_S = 1 MS/s
- ADC_ACR.IBCTL = (01)₂

Table 11-64. Static Performance Characteristics⁽¹⁾
Symbol	Parameter	Min	Max	Unit
RES_ADC	Native ADC resolution	12		Bit
INL	Integral non-linearity	-3	3	LSB
DNL	Differential non-linearity	-2	2	LSB
OE	Offset error⁽²⁾	-7	4	LSB
OE_AT	Offset error in Autotest mode (ADC_EMR.ADCMODE≠0)⁽³⁾	-10	10	LSB
GE	Gain error⁽²⁾	-7	4	LSB
GE_AT	Gain error in Autotest mode (ADC_EMR.ADCMODE≠0)⁽³⁾	-10	10	LSB

Note: