6.4.7.15 ISC Defective Pixel Control Register
This register can only be written if WPCREN is cleared in ISC_WPMR.
| Name: | ISC_DPC_CTRL |
| Offset: | 0x40 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BLCEN | GDCEN | DPCEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – BLCEN Black Level Correction Enable
| Value | Description |
|---|---|
| 0 | Black level correction is disabled. |
| 1 | Black level correction is enabled. |
Bit 1 – GDCEN Green Disparity Correction Enable
| Value | Description |
|---|---|
| 0 | Green disparity correction is disabled. |
| 1 | Green disparity correction is enabled. |
Bit 0 – DPCEN Defective Pixel Correction Enable
| Value | Description |
|---|---|
| 0 |
Defective pixel correction is disabled. |
| 1 |
Defective pixel correction is enabled. |