4.6.1 I2C Client Timing

The I2C Client timing diagram for the ATWILC3000-MR110xA module is shown in the following figure.

Figure 4-1. I2C Client Timing Diagram

The following table provides the I2C Client timing parameters for the ATWILC3000-MR110xA module.

Table 4-9. I2C Client Timing Parameters
ParameterSymbolMin.Max.UnitsRemarks
SCL Clock FrequencyfSCL0400kHz
SCL Low Pulse WidthtWL1.3µs
SCL High Pulse WidthtWH0.6
SCL, SDA Fall TimetHL300ns
SCL, SDA Rise TimetLH300This is dictated by external components
START Setup TimetSUSTA0.6µs
START Hold TimetHDSTA0.6
SDA Setup TimetSUDAT100ns
SDA Hold TimetHDDAT0nsClient and Host Default
40µsHost Programming Option
STOP Setup TimetSUSTO0.6µs
Bus Free Time Between STOP and STARTtBUF1.3
Glitch Pulse RejecttPR050ns