4.6.2 SPI Client Timing

The SPI Client timing for the ATWILC3000-MR110xA module is provided in the following figures.

Figure 4-2. SPI Client Timing Diagram

The following table provides the SPI Client timing parameters for the ATWILC3000-MR110xA module.

Table 4-10. SPI Client Timing Parameters (1)
ParameterSymbolMin.Max.Unit
Clock Input Frequency (2)fSCK48MHz
Clock Low Pulse WidthtWL6ns
Clock High Pulse WidthtWH4
Clock Rise TimetLH07
Clock Fall TimetHL07
TXD Output Delay (3)tODLY39 from SCK fall
RXD Input Setup TimetISU3
RXD Input Hold TimetIHD5
SSN Input Setup TimetSUSSN5
SSN Input Hold TimetHDSSN5
Note:
  1. The timing is applicable to all SPI modes.
  2. The maximum clock frequency specified is limited by the SPI Client interface internal design; the actual maximum clock frequency can be lower and depends on the specific PCB layout.
  3. The timing is based on 15 pF output loading. Under all conditions, tLH + tWH + tHL + tWL must be less than or equal to 1/ fSCK.