5.3.2.1 Parameters

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Coefficients are loaded using INIT parameter. It holds the 16 x 18 ROM content as a linear array. The first 18 bits are word 0, the next 18 bits are word 1, and so on. The following table lists the INIT declaration for loading coefficients.

Table 5-16. MACC_PA_BC_ROM Parameter Descriptions
Parameter	Dimensions	Description
INIT	parameter [287:0] INIT = { 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0, 18'h0 };	16 x 18 ROM content specified in Verilog.
INIT	generic map(INIT => ( B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”& B“00_0000_0000_0000_0000”) )	16 x 18 ROM content specified in VHDL.