5.3.2.2 Port List
(Ask a Question)| Port Name | Direction | Type1 | Polarity | Description |
|---|---|---|---|---|
| DOTP | Input | Static | Active high | DOTP mode. When DOTP = 1, MACC_PA_BC_ROM block performs DOTP of two pairs of 9-bit operands. SIMD must not be 1. C[8:0] must be connected to CARRYIN. |
| SIMD | Input | Static | Active high | SIMD mode When SIMD = 1, MACC_PA_BC_ROM block performs dual independent multiplication of two pairs of 9-bit operands. DOTP must not be 1 ARSHFT17 must be 0 D[8:0] must be 0 C[17:0] must be 0 E[17:0] must be 0. For information on how operand E is obtained from P, CDIN or 0, see Table 3-3. |
| OVFL_CARRYOUT_SEL | Input | Static | Active high | Generate OVERFLOW or CARRYOUT with result
P. OVERFLOW when OVFL_CARRYOUT_SEL = 0 CARRYOUT when OVFL_CARRYOUT_SEL = 1 |
| CLK | Input | Dynamic | Rising edge | Clock for A, B, C, CARRYIN, D, P, OVFL_CARRYOUT, ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers. |
| AL_N | Input | Dynamic | Active low | Asynchronous load for A, B, P, OVFL_CARRYOUT,
ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers. Connect to 1, if none are
registered. When asserted, A, B, P, and OVFL_CARRYOUT registers are loaded with zero, while the ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers are loaded with the complementary value of the respective _AD_N. |
| USE_ROM | Input | Static (virtual) | Active high | Selection for operand A. When USE_ROM = 0, select input data A. When USE_ROM = 1, select ROM data at ROM_ADDR. |
| ROM_ADDR[3:0] | Input | Dynamic | Active high | Address of ROM data for operand A when USE_ROM = 1 |
| A[17:0] | Input | Dynamic | Active high | Input data for operand A when USE_ROM = 0 |
| A_BYPASS | Input | Static | Active high | Bypass data A registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| A_SRST_N | Input | Dynamic | Active low | Synchronous reset for data A registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| A_EN | Input | Dynamic | Active high | Enable for data A registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| B[17:0] | Input | Dynamic | Active high | Input data B to pre-adder with data D |
| B_BYPASS | Input | Static | Active high | Bypass data B registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| B_SRST_N | Input | Dynamic | Active low | Synchronous reset for data B registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| B_EN | Input | Dynamic | Active high | Enable for data B registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| B2[17:0] | Output | Dynamic | Active high | Pipelined output of input data B. Result P must be floating when B2 is used. |
| B2_BYPASS | Input | Static | Active high | Bypass data B2 registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| B2_SRST_N | Input | Dynamic | Active low | Synchronous reset for data B2 registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| B2_EN | Input | Dynamic | Active high | Enable for data B2 registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| BCOUT[17:0] | Output | Cascade | Active high | Cascade output of B2. Value of BCOUT is the same as B2. The entire bus must either be dangling or drive an entire B input of another MACC_PA or MACC_PA_BC_ROM block. |
| D[17:0] | Input | Dynamic | Active high | Input data D to pre-adder with data B. When SIMD = 1, connect D[8:0] to 0. |
| D_BYPASS | Input | Static | Active high | Bypass data D registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| D_ARST_N | Input | Dynamic | Active low | Asynchronous reset for data D registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| D_SRST_N | Input | Dynamic | Active low | Synchronous reset for data D registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| D_EN | Input | Dynamic | Active high | Enable for data D registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| CARRYIN | Input | Dynamic | Active high | CARRYIN for input data C |
| C[47:0] | Input | Dynamic | Active high | Input data C. When DOTP = 1, connect C[8:0] to CARRYIN. When SIMD = 1, connect C[8:0] to 0. |
| C_BYPASS | Input | Static | Active high | Bypass CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| C_ARST_N | Input | Dynamic | Active low | Asynchronous reset for CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| C_SRST_N | Input | Dynamic | Active low | Synchronous reset for CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| C_EN | Input | Dynamic | Active high | Enable for CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15. |
| CDIN[47:0] | Input | Cascade | Active high | Cascaded input for operand E. The entire bus must be driven by an entire CDOUT of another MACC_PA or MAC_PA_BC_ROM block. In Dot-product mode, the driving CDOUT must also be generated by a MACC_PA or MAC_PA_BC_ROM block in Dot-product mode. For more information about how CDIN is propagated to operand E, see Table 3-3. |
| P[47:0] | Output | — | Active high | Result data. For more information, see Table 3-3. B2 output must be floating when P is used. |
| OVFL_CARRYOUT | Output | — | Active high | OVERFLOW or CARRYOUT. For more information, see Table 3-2. |
| P_BYPASS | Input | Static | Active high | Bypass P and OVFL_CARRYOUT registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| P_SRST_N | Input | Dynamic | Active low | Synchronous reset for P and OVFL_CARRYOUT registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| P_EN | Input | Dynamic | Active high | Enable for P and OVFL_CARRYOUT registers. Connect to 1 if not registered. For more information, see Table 5-14. |
| CDOUT[47:0] | Output | Cascade | Active high | Cascade output of result P. For more
information, see Table 3-4. Value of CDOUT is the same as P. The entire bus must either be dangling or drive an entire CDIN of another MACC_PA or MAC_PA_BC_ROM block in cascaded mode. |
| PASUB | Input | Dynamic | Active high | Subtract operation for pre-adder of B and D |
| PASUB_BYPASS | Input | Static | Active high | Bypass PASUB register. Connect to 1 if not registered. For more information, see Table 5-13. |
| PASUB_AD_N | Input | Static | Active low | Asynchronous load data for PASUB register. For more information, see Table 5-13. |
| PASUB_SL_N | Input | Dynamic | Active low | Synchronous load for PASUB register. Connect to 1 if not registered. For more information, see Table 5-13. |
| PASUB_SD_N | Input | Static | Active low | Synchronous load data for PASUB register. For more information, see Table 5-13. |
| PASUB_EN | Input | Dynamic | Active high | Enable for PASUB register. Connect to 1 if not registered. For more information, see Table 5-13. |
| CDIN_FDBK_SEL[1:0] | Input | Dynamic | Active high | Select CDIN, P or 0 for operand E. For more information, see Table 3-3. |
| CDIN_FDBK_SEL_BYPASS | Input | Static | Active high | Bypass CDIN_FDBK_SEL register. Connect to 1 if not registered. For more information, see Table 5-13. |
| CDIN_FDBK_SEL_AD_N [1:0] | Input | Static | Active low | Asynchronous load data for CDIN_FDBK_SEL register. For more information, see Table 5-13. |
| CDIN_FDBK_SEL_SL_N | Input | Dynamic | Active low | Synchronous load for CDIN_FDBK_SEL register. Connect to 1 if not registered. For more information, see Table 5-13. |
| CDIN_FDBK_SEL_SD_N [1:0] | Input | Static | Active low | Synchronous load data for CDIN_FDBK_SEL register. For more information, see Table 5-13. |
| CDIN_FDBK_SEL_EN | Input | Dynamic | Active high | Enable for CDIN_FDBK_SEL register. Connect to 1 if not registered. For more information, see Table 5-13. |
| ARSHFT17 | Input | Dynamic | Active high | Arithmetic right-shift for operand E. When asserted, a 17-bit arithmetic right-shift is performed on operand E. For more information about how operand E is obtained from P, CDIN or 0, see Table 3-3. When SIMD = 1, ARSHFT17 must be 0. |
| ARSHFT17_BYPASS | Input | Static | Active high | Bypass ARSHFT17 register. Connect to 1, if not registered. For more information, see Table 5-13. |
| ARSHFT17_AD_N | Input | Static | Active low | Asynchronous load data for ARSHFT17 register. For more information, see Table 5-13. |
| ARSHFT17_SL_N | Input | Dynamic | Active low | Synchronous load for ARSHFT17 register. Connect to 1 if not registered. For more information, see Table 5-13. |
| ARSHFT17_SD_N | Input | Static | Active low | Synchronous load data for ARSHFT17 register. For more information, see Table 5-13. |
| ARSHFT17_EN | Input | Dynamic | Active high | Enable for ARSHFT17 register. Connect to 1 if not registered. For more information, see Table 5-13. |
| SUB | Input | Dynamic | Active high | Subtract operation |
| SUB_BYPASS | Input | Static | Active high | Bypass SUB register. Connect to 1 if not registered. For more information, see Table 5-13. |
| SUB_AD_N | Input | Static | Active low | Asynchronous load data for SUB register. For more information, see Table 5-13. |
| SUB_SL_N | Input | Dynamic | Active low | Synchronous load for SUB register. Connect to 1 if not registered. For more information, see Table 5-13. |
| SUB_SD_N | Input | Static | Active low | Synchronous load data for SUB register. For more information, see Table 5-13. |
| SUB_EN | Input | Dynamic | Active high | Enable for SUB register. Connect to 1 if not registered. For more information, see Table 5-13. |
|
Note: (1) Static inputs are defined at design time
and need to be tied to 0 or 1.
|