22.9.7 Peripheral Clock Generator 2
The CFGPCLKGEN2 dictates the peripheral clock selection described in the Clock and Reset Unit chapter. See Clock and Reset Unit (CRU) from Related Links.
There is no Flash location for this register because the purpose of this register is to provide an application-based peripheral clocking selection. This is best handled in the application software drivers.
| Name: | CFGPCLKGEN2 |
| Offset: | 0x70 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EVSYSC8CD | EVSYSC8SEL[2:0] | EVSYSC7CD | EVSYSC7SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EVSYSC6CD | EVSYSC6SEL[2:0] | EVSYSC5CD | EVSYSC5SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EVSYSC4CD | EVSYSC4SEL[2:0] | EVSYSC3CD | EVSYSC3SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVSYSC2CD | EVSYSC2SEL[2:0] | EVSYSC1CD | EVSYSC1SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – EVSYSC8CD EVSYS Channel 8 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 30:28 – EVSYSC8SEL[2:0] EVSYS Channel 8 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 27 – EVSYSC7CD EVSYS Channel 7 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 26:24 – EVSYSC7SEL[2:0] EVSYS Channel 7 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 23 – EVSYSC6CD EVSYS Channel 6 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 22:20 – EVSYSC6SEL[2:0] EVSYS Channel 6 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 19 – EVSYSC5CD EVSYS Channel 5 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 18:16 – EVSYSC5SEL[2:0] EVSYS Channel 5 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 15 – EVSYSC4CD EVSYS Channel 4 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 14:12 – EVSYSC4SEL[2:0] EVSYS Channel 4 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 11 – EVSYSC3CD EVSYS Channel 3 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 10:8 – EVSYSC3SEL[2:0] EVSYS Channel 3 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 7 – EVSYSC2CD EVSYS Channel 2 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 6:4 – EVSYSC2SEL[2:0] EVSYS Channel 2 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 3 – EVSYSC1CD EVSYS Channel 1 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 2:0 – EVSYSC1SEL[2:0] EVSYS Channel 1 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |