22.9.1 Configuration Control Register 0

The CFGLOCK[1:0] register bits are writable only when CFGLOCK[0] = 0.

The IOLOCK, PMDLOCK and PGLOCK register bits can only be cleared on a system Reset. Thereafter, these bits are writable using CFGLOCK.

This register is loaded with trusted data from FBCFG1/DEVCFG0 during the pre-boot period. Trusted data from Flash means that when there is no BCFG* fail status and BINFOVALID = 0 during Flash, the configuration word reads. If accompanied by the fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained and new values from FBCFG1 are not loaded.

Under all conditions, Flash loading is omitted for the following bits in the CFGCON0 register:
  • IOLOCK
  • CFGLOCK[1:0]
  • PMDLOC
  • PGLOCK
  • PMULOCK
  • JTAGEN
  • HPLUGDIS

Hence, writing these bits in Boot Flash does not have an effect on the configuration register.

Name: CFGCON0(L)
Offset: 0x00
Reset: 0x7100000b
Property: -

Bit 3130292827262524 
  FRECCDISECCCTL[1:0] INT0PINT0EPCM 
Access R/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 111001 
Bit 2322212019181716 
 SLRTEN2SLRTEN1SLRTEN0HPLUGDISSMBUSEN2SMBUSEN1SMBUSEN0  
Access R/W/LR/W/LR/W/LR/WR/W/LR/W/LR/W/L 
Reset 0000000 
Bit 15141312111098 
 CFGLOCK[1:0]IOLOCKPMDLOCKPGLOCKPMULOCKRTCOUT_ALTENRTCIN0_ALTEN 
Access R/W/LR/W/LR/S/LR/S/LR/S/LR/S/LR/W/LR/W/L 
Reset 00000000 
Bit 76543210 
 CPENFILTACCMP1_ALTEN ADCPOVRJTAGENTROENSWOEN  
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 000101 

Bit 30 – FRECCDIS Flex RAM (SRAM) ECC Control

Note: Only a read-only fuse bit sets the initialization value of RAMECC Control. The true RAMECC override is available in the RAMECC module.
ValueDescription
1ECC is disabled
0ECC is enabled

Bits 29:28 – ECCCTL[1:0] Flash ECC Control

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
11ECC and dynamically ECC are disabled
10ECC and dynamically ECC are disabled
01Dynamically ECC is enabled
00ECC is enabled (NVMCON.NVMOP[3:0] != 1 (Word programming))

Bit 26 – INT0P INT0P Polarity

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1INT0 Polarity (High)
0INT0 Polarity (Low)

Bit 25 – INT0E INT0 Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1INT0 is enabled
0INT0 is disabled

Bit 24 – PCM PCHE I/D Cacheable Mode

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Always enabled from outside. Can be further enabled/disabled by PCHE SFR registers.
0The cache-ability is controlled by the CPU via HPROT[3] of ARM protection control bus.

Bit 23 – SLRTEN2 Slew Rate Enable for SERCOM2

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Slew rate is enabled
0Slew rate is disabled

Bit 22 – SLRTEN1 Slew Rate Enable for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Slew rate is enabled
0Slew rate is disabled

Bit 21 – SLRTEN0 Slew Rate Enable for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Slew rate is enabled
0Slew rate is disabled

Bit 20 – HPLUGDIS Hot Plugging Disable (outside fuse loading)

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Hot plugging is disabled
0Hot plugging is enabled

Bit 19 – SMBUSEN2 SMBus Enable for SERCOM2

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1SMBus is enabled
0SMBus is disabled

Bit 18 – SMBUSEN1 SMBus Enable for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1SMBus is enabled
0SMBus is disabled

Bit 17 – SMBUSEN0 SMBus Enable for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1SMBus is enabled
0SMBus is disabled

Bits 15:14 – CFGLOCK[1:0] Configuration Register Lock

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’ or ‘10’.
ValueDescription
11All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are locked and cannot be written. CFGLOCK value cannot be changed.
10All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are locked and cannot be written. CFGLOCK value can be changed.
01Reserved for future use
00All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are not locked and can be written. CFGLOCK value can be changed.

Bit 13 – IOLOCK I/O Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1I/O Remap SFR bits are locked and cannot be modified
0I/O Remap SFR bits are not locked and can be modified

Bit 12 – PMDLOCK Peripheral Module Disable (PMD) Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1PMDx SFR bits are locked and cannot be modified
0PMDx SFR bits are not locked and can be modified

Bit 11 – PGLOCK Permission Group Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1CFGPG SFR bits are locked and cannot be modified
0CFGPG SFR bits are not locked and can be modified

Bit 10 – PMULOCK PMU Controller Register Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1PMU* SFR bits are locked and cannot be modified
0PMU* SFR bits are not locked and can be modified

Bit 9 – RTCOUT_ALTEN RTCOUT Alternate Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1RTC/OUT is available on PA10
0RTC/OUT is available on PA4

Bit 8 – RTCIN0_ALTEN RTCIN0 Alternate Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1RTC_IN0 is available on PA9
0RTC_IN0 is available on PA3

Bit 7 – CPENFILT ADC CP Filter Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1ADC CP filter is enabled
0ADC CP filter is disabled

Bit 6 – ACCMP1_ALTEN AC CMP1 Alternate Enable

Note:
  • This bit is only writable when CFGLOCK[1:0] is ‘00’.
  • For the 32-pin variant PIC32CX5109BZ31032 device, this bit is set to be ‘0’.
ValueDescription
1AC_CMP1 Out is available on PA6
0AC_CMP1 Out is available on PA13

Bit 4 – ADCPOVR ADC Charge Pump Override

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Overridden (Software controlled)
0Hardware controlled

Bit 3 – JTAGEN JTAG Enable

Note: JTAG functionality is not available in the PIC32CX-BZ3 devices. The default value of this bit is ‘1’. It is recommended to write ‘0’ to this bit during Application initialization to use JTAG pins for regular GPIO functionality. For pin details, see I/O Ports and Peripheral Pin Select (PPS) from Related Links.

Bit 2 – TROEN Trace Output Enable

Note:
  • When CFGCON1.TRCEN = 0, the value of this bit is ignored but has the effect of being ‘0’.
  • This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Start Trace Clock and enable Trace Outputs (Trace probe must be present)
0Stop Trace Clock and disable Trace Outputs

Bit 1 – SWOEN SWO Enable on two-wire Debug interface

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1SWO is enabled
0SWO is disabled