22.9.5 Permission Group Configuration
All bits in this register are writable only when CFGCON0.PGLOCK = 0.
There is no Flash location for this register because the purpose of this register to provide software based protection mechanism to device memory mapped region.
Name: | CFGPGQOS |
Offset: | 0x50 |
Reset: | 0xe044004c |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
WISIBQOS[1:0] | FCQOS[1:0] | DSUPG[1:0] | |||||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |||
Reset | 1 | 1 | 1 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CRYPTOQOS[1:0] | CRYPTOPG[1:0] | ||||||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | |||||
Reset | 0 | 1 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DMAPG[1:0] | |||||||||
Access | R/W/L | R/W/L | |||||||
Reset | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CPUQOS[1:0] | CPUPG[1:0] | ||||||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | |||||
Reset | 1 | 1 | 0 | 0 |
Bits 31:30 – WISIBQOS[1:0] Wireless SIB QOS Control Bits
Note: This field is only writable when CFGCON0.PGLOCK
= 0.
Value | Description |
---|---|
00 | Disable; Background |
01 | Low; Sensitive bandwidth |
10 | Medium; Sensitive latency |
11 | High; Critical latency |
Bits 29:28 – FCQOS[1:0] FC Controller QOS Control Bits
Note: This field is only writable when CFGCON0.PGLOCK
= 0.
Value | Description |
---|---|
00 | Disable; Background |
01 | Low; Sensitive bandwidth |
10 | Medium; Sensitive latency |
11 | High; Critical latency |
Bits 25:24 – DSUPG[1:0] DSU Permission Group
- DSUPG[1:0] ==
2’b11
: Initiator is assigned to Permission Group 3 - DSUPG[1:0] ==
2’b10
: Initiator is assigned to Permission Group 2 - DSUPG[1:0] ==
2’b01
: Initiator is assigned to Permission Group 1 - DSUPG[1:0] ==
2’b00
: Initiator is assigned to Permission Group 0
Note: This field is only
writable when CFGCON0.PGLOCK = 0.
Bits 23:22 – CRYPTOQOS[1:0] Crypto QOS Control Bits
Note: This field is only writable when CFGCON0.PGLOCK
= 0.
Value | Description |
---|---|
00 | Disable; Background |
01 | Low; Sensitive bandwidth |
10 | Medium; Sensitive latency |
11 | High; Critical latency |
Bits 21:20 – CRYPTOPG[1:0] Crypto Permission Group
- CRYPTOPG[1:0] ==
2’b11
: Initiator is assigned to Permission Group 3 - CRYPTOPG[1:0] ==
2’b10
: Initiator is assigned to Permission Group 2 - CRYPTOPG[1:0] ==
2’b01
: Initiator is assigned to Permission Group 1 - CRYPTOPG[1:0] ==
2’b00
: Initiator is assigned to Permission Group 0
Note: This field is only
writable when CFGCON0.PGLOCK = 0.
Bits 9:8 – DMAPG[1:0] DMA (Rd/Wr) Permission Group
- DMAPG[1:0] ==
2’b11
: Initiator is assigned to Permission Group 3 - DMAPG[1:0] ==
2’b10
: Initiator is assigned to Permission Group 2 - DMAPG[1:0] ==
2’b01
: Initiator is assigned to Permission Group 1 - DMAPG[1:0] ==
2’b00
: Initiator is assigned to Permission Group 0
Note: This field is only
writable when CFGCON0.PGLOCK = 0.
Bits 3:2 – CPUQOS[1:0] CPU I/D and System Bus QOS Control Bits
Note: This field is only writable when CFGCON0.PGLOCK
= 0.
Value | Description |
---|---|
00 | Disable; Background |
01 | Low; Sensitive bandwidth |
10 | Medium; Sensitive latency |
11 | High; Critical latency |
Bits 1:0 – CPUPG[1:0] CPU (Code) Permission Group
- CPUPG[1:0] ==
2’b11
: Initiator is assigned to Permission Group 3 - CPUPG[1:0] ==
2’b10
: Initiator is assigned to Permission Group 2 - CPUPG[1:0] ==
2’b01
: Initiator is assigned to Permission Group 1 - CPUPG[1:0] ==
2’b00
: Initiator is assigned to Permission Group 0
Note:
- CPUPG[1:0] automatically reverts to
2’b00
when the CPU acknowledges entering into an NMI exception - This field is only writable when CFGCON0.PGLOCK =
0
.