22.9.9 Peripheral Clock Generator 4
The CFGPCLKGEN4 dictates the peripheral clock selection described in the Clock and Reset Unit chapter. See Clock and Reset Unit (CRU) from Related Links.
There is no Flash location for this register because the purpose of this register is to provide an application-based peripheral clocking selection. This is best handled in the application software drivers.
| Name: | CFGPCLKGEN4 |
| Offset: | 0x90 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TC67CD | TC67CSEL[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TC45CD | TC45CSEL[2:0] | TC23CD | TC23CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TC1CD | TC1CSEL[2:0] | TC0CD | TC0CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 19 – TC67CD TC6 and TC7 Peripheral Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 18:16 – TC67CSEL[2:0] TC6 and TC7 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 15 – TC45CD TC4 and TC5 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 14:12 – TC45CSEL[2:0] TC4 and TC5 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 11 – TC23CD TC2 and TC3 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 10:8 – TC23CSEL[2:0] TC2 and TC3 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 7 – TC1CD TC1 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 6:4 – TC1CSEL[2:0] TC1 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 3 – TC0CD TC0 Clock Enable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 2:0 – TC0CSEL[2:0] TC0 Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 is clock selected |
| 7 | Low power clock is selected |