22.9.4 Configuration Control Register 4
This register is loaded with trusted data from FBCFG4/DEVCFG4 during the pre-boot period.
Trusted data from Flash means that when there is no BCFG* fail status during Flash, configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained and new values from FBCFG4 are not loaded.
Name: | CFGCON4(L) |
Offset: | 0x40 |
Reset: | 0x840e4000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
RTCNTM_CSEL | LPOSCEN | UVREGROVR | DSBITEN | DSWDTEN | DSWDTLPRC | DSWDTPS[4:3] | |||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
Reset | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DSWDTPS[2:0] | DSZPBOREN | CPEN_DLY[2:0] | RTCEVTYPE | ||||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
Reset | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
MLPCLK_MOD | VBKP_DIVSEL | VBKP_32KCSEL[1:0] | VBKP_1KCSEL | RTCEVENT_EN | RTCEVENTSEL[1:0] | ||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SOSC_CFG[7:0] | |||||||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – RTCNTM_CSEL RTCC Counter Mode Clock Select
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Raw 32 KHz clock |
0 | Processed 32 KHz clock |
Bit 30 – LPOSCEN Low Power (Secondary) Oscillator Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Enable Low Power (Secondary) Oscillator, also at Reset |
0 | Disable Low Power (Secondary) Oscillator |
Bit 29 – UVREGROVR ULPVREG Retention Mode Override
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | ULPVREG forced in the Retention mode |
0 | ULPVREG controlled by XDS/DS FSM |
Bit 28 – DSBITEN Deep Sleep Bit Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Enable DS bit in DSCON |
0 | Disable DS bit in DSCON |
Bit 27 – DSWDTEN Deep Sleep Watchdog Timer Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Enable DSWDT during deep sleep |
0 | Disable DSWDT during deep sleep |
Bit 26 – DSWDTLPRC Deep Sleep Watchdog Timer Reference Clock Select
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Select LPRC as DSWDT reference clock |
0 | Select SOSC as DSWDT reference clock |
Bits 25:21 – DSWDTPS[4:0] Deep Sleep Watchdog Timer Postscale Select
Note: These bits are only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
11111 | 1:236 (25.7 days) |
11110 | 1:235 (12.8 days) |
11101 | 1:234 (6.4 days) |
11100 | 1:233 (77.0 hours) |
11011 | 1:232 (38.5 hours) |
11010 | 1:231 (19.2 hours) |
11001 | 1:230 (9.6 hours) |
11000 | 1:229 (4.8 hours) |
10111 | 1:228 (2.4 hours) |
10110 | 1:227 (72.2 minutes) |
10101 | 1:226 (36.1 minutes) |
10100 | 1:225 (18.0 minutes) |
10011 | 1:224 (9.0 minutes) |
10010 | 1:223 (4.5 minutes) |
10001 | 1:222 (135.3 s) |
10000 | 1:221 (67.7 s) |
01111 | 1:220 (33.825 s) |
01110 | 1:219 (16.912 s) |
01101 | 1:218 (8.456 s) |
01100 | 1:217 (4.228 s) |
01011 | 1:65536 (2.114 s) |
01010 | 1:32768 (1.057 s) |
01001 | 1:16384 (528.5 ms) |
01000 | 1:8192 (264.3 ms) |
00111 | 1:4096 (132.1 ms) |
00110 | 1:2048 (66.1 ms) |
00101 | 1:1024 (33 ms) |
00100 | 1:512 (16.5 ms) |
00011 | 1:256 (8.3 ms) |
00010 | 1:128 (4.1 ms) |
00001 | 1:64 (2.1 ms) |
00000 | 1:32 (1 ms) |
Bit 20 – DSZPBOREN Deep Sleep Zero-Power BOR Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Enable ZPBOR during deep sleep |
0 | Disable ZPBOR during deep sleep |
Bits 19:17 – CPEN_DLY[2:0] Charge-pump Ready Digital Delay (Safety Delay to Analog CP Ready)
Note: These bits are only writable when CFGLOCK[1:0] is ‘
00
’.Bit 16 – RTCEVTYPE RTCC Event Type
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | RTC_EVENT |
0 | RTC_OUT |
Bit 15 – MLPCLK_MOD LPCLK Modifier in Counter/Delay Mode
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Divide-by 1.024 (Recommended when LPCLK = 32.768 KHz) |
0 | Divide-by 1 (Recommended when LPCLK = 32 KHz) |
Bit 14 – VBKP_DIVSEL VDDBUKPCORE LPCLK Clock Divider Selection
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Divide by 31.25 (Recommended when LPCLK = 32 KHz) |
0 | Divide-by 32 (Recommended when LPCLK = 32.768 KHz) |
Bits 13:12 – VBKP_32KCSEL[1:0] VDDBUKPCORE 32 KHz Clock Source Selection
Note:
- When ‘
00
’ or ‘01
’, the Deep Sleep mode is entered and it falls back to ‘11
’ before entering Deep Sleep. Any change of clock source results in gaps in the LPCLK output. - These bits are only writable when CFGLOCK[1:0] is ‘
00
’.
Value | Description |
---|---|
11 | LPRC |
10 | SOSC |
01 | POSC |
00 | FRC |
Bit 11 – VBKP_1KCSEL VDDBUKPCORE LPCLK Clock Selection
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Divide by 32 or 31.25 clock depending on VBKP_DIVSEL |
0 | 32 KHz low power clock |
Bit 10 – RTCEVENT_EN Output Enable for RTCC Event Output
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
1 | Enables RTCC-Event output |
0 | Disables RTCC-Event output |
Bits 9:8 – RTCEVENTSEL[1:0] RTCC Event Selection
Note: These bits are only writable when CFGLOCK[1:0] is ‘
00
’.Value | Description |
---|---|
00 | 1-Second clock |
01 | Alarm pulse |
1x | 32 KHz clock |
Bits 7:0 – SOSC_CFG[7:0] SOSC Configuration Bits
Gain configuration for SOSC Oscillator:
G3>G2>G1>G0
- 11 = Gain is G3
- 10 = Gain is G2
- 01 = Gain is G1
- 00 = Gain is G0
Note: These bits are only writable when CFGLOCK[1:0] is ‘
00
’.