22.9.4 Configuration Control Register 4

This register is loaded with trusted data from FBCFG4/DEVCFG4 during the pre-boot period.

Trusted data from Flash means that when there is no BCFG* fail status during Flash, configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained and new values from FBCFG4 are not loaded.

Name: CFGCON4(L)
Offset: 0x40
Reset: 0x840e4000
Property: -

Bit 3130292827262524 
 RTCNTM_CSELLPOSCENUVREGROVRDSBITENDSWDTENDSWDTLPRCDSWDTPS[4:3] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 10000100 
Bit 2322212019181716 
 DSWDTPS[2:0]DSZPBORENCPEN_DLY[2:0]RTCEVTYPE 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 00001110 
Bit 15141312111098 
 MLPCLK_MODVBKP_DIVSELVBKP_32KCSEL[1:0]VBKP_1KCSELRTCEVENT_ENRTCEVENTSEL[1:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 01000000 
Bit 76543210 
 SOSC_CFG[7:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 00000000 

Bit 31 – RTCNTM_CSEL RTCC Counter Mode Clock Select

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Raw 32 KHz clock
0Processed 32 KHz clock

Bit 30 – LPOSCEN Low Power (Secondary) Oscillator Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Enable Low Power (Secondary) Oscillator, also at Reset
0Disable Low Power (Secondary) Oscillator

Bit 29 – UVREGROVR ULPVREG Retention Mode Override

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1ULPVREG forced in the Retention mode
0ULPVREG controlled by XDS/DS FSM

Bit 28 – DSBITEN Deep Sleep Bit Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Enable DS bit in DSCON
0Disable DS bit in DSCON

Bit 27 – DSWDTEN Deep Sleep Watchdog Timer Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Enable DSWDT during deep sleep
0Disable DSWDT during deep sleep

Bit 26 – DSWDTLPRC Deep Sleep Watchdog Timer Reference Clock Select

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Select LPRC as DSWDT reference clock
0Select SOSC as DSWDT reference clock

Bits 25:21 – DSWDTPS[4:0] Deep Sleep Watchdog Timer Postscale Select

The DS WDT prescaler is 32; this creates an approximate base time unit of 1 ms.
Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
111111:236 (25.7 days)
111101:235 (12.8 days)
111011:234 (6.4 days)
111001:233 (77.0 hours)
110111:232 (38.5 hours)
110101:231 (19.2 hours)
110011:230 (9.6 hours)
110001:229 (4.8 hours)
101111:228 (2.4 hours)
101101:227 (72.2 minutes)
101011:226 (36.1 minutes)
101001:225 (18.0 minutes)
100111:224 (9.0 minutes)
100101:223 (4.5 minutes)
100011:222 (135.3 s)
100001:221 (67.7 s)
011111:220 (33.825 s)
011101:219 (16.912 s)
011011:218 (8.456 s)
011001:217 (4.228 s)
010111:65536 (2.114 s)
010101:32768 (1.057 s)
010011:16384 (528.5 ms)
010001:8192 (264.3 ms)
001111:4096 (132.1 ms)
001101:2048 (66.1 ms)
001011:1024 (33 ms)
001001:512 (16.5 ms)
000111:256 (8.3 ms)
000101:128 (4.1 ms)
000011:64 (2.1 ms)
000001:32 (1 ms)

Bit 20 – DSZPBOREN Deep Sleep Zero-Power BOR Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Enable ZPBOR during deep sleep
0Disable ZPBOR during deep sleep

Bits 19:17 – CPEN_DLY[2:0] Charge-pump Ready Digital Delay (Safety Delay to Analog CP Ready)

n = (n+1) LPRC Clock Cycle Delay
Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.

Bit 16 – RTCEVTYPE RTCC Event Type

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1RTC_EVENT
0RTC_OUT

Bit 15 – MLPCLK_MOD LPCLK Modifier in Counter/Delay Mode

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Divide-by 1.024 (Recommended when LPCLK = 32.768 KHz)
0Divide-by 1 (Recommended when LPCLK = 32 KHz)

Bit 14 – VBKP_DIVSEL VDDBUKPCORE LPCLK Clock Divider Selection

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Divide by 31.25 (Recommended when LPCLK = 32 KHz)
0Divide-by 32 (Recommended when LPCLK = 32.768 KHz)

Bits 13:12 – VBKP_32KCSEL[1:0] VDDBUKPCORE 32 KHz Clock Source Selection

Note:
  • When ‘00’ or ‘01’, the Deep Sleep mode is entered and it falls back to ‘11’ before entering Deep Sleep. Any change of clock source results in gaps in the LPCLK output.
  • These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
11LPRC
10SOSC
01POSC
00FRC

Bit 11 – VBKP_1KCSEL VDDBUKPCORE LPCLK Clock Selection

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Divide by 32 or 31.25 clock depending on VBKP_DIVSEL
032 KHz low power clock

Bit 10 – RTCEVENT_EN Output Enable for RTCC Event Output

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Enables RTCC-Event output
0Disables RTCC-Event output

Bits 9:8 – RTCEVENTSEL[1:0] RTCC Event Selection

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
001-Second clock
01Alarm pulse
1x32 KHz clock

Bits 7:0 – SOSC_CFG[7:0] SOSC Configuration Bits

Gain configuration for SOSC Oscillator:

G3>G2>G1>G0

  • 11 = Gain is G3
  • 10 = Gain is G2
  • 01 = Gain is G1
  • 00 = Gain is G0
Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.