30.8.4 Channel Pending Interrupt
An interrupt that handles several channels must consult the INTPEND register to find out which channel number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated to only one channel must not use the INTPEND register.
| Name: | INTPEND |
| Offset: | 0x10 |
| Reset: | 0x4000 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BUSY | READY | EVD | OVR | ||||||
| Access | R | R | RW | RW | |||||
| Reset | 0 | 1 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ID[3:0] | |||||||||
| Access | RW | RW | RW | RW | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 15 – BUSY Busy
1’ when the event on a channel selected by the Channel ID field (ID) was not handled by all the event users connected to this channel.Bit 14 – READY Ready
1’ when all event users connected to the channel selected by the Channel ID field (ID) are ready to handle incoming events on this channel.Bit 9 – EVD Channel Event Detected
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request is generated if CHINTENCLR/SET.EVD is ‘1’.
When the event channel path is asynchronous, the EVD bit will not be set.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears it. It also clears the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn) of this peripheral, where n is determined by the Channel ID bit field (ID) in this register.
Bit 8 – OVR Channel Overrun
This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request is generated if CHINTENCLR/SET.OVRx is ‘1’.
There are two possible overrun channel conditions:
- One or more of the event users on the channel selected by the Channel ID field (ID) are not ready when a new event occurs
- An event happens when all the event users have not yet handled the previous event on the channel selected by the Channel ID field (ID)
When the event channel path is asynchronous, the OVR interrupt flag will not be set.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears it. It also clears the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn) of this peripheral, where n is determined by the Channel ID bit field (ID) in this register.
Bits 3:0 – ID[3:0] Channel ID
These bits store the channel number of the highest priority.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.