34.10.10 Address

Name: ADDR
Offset: 0x24
Reset: 0x0000
Property: Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 LEN[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 TENBITEN LENEN  ADDR[10:8] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 ADDR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 23:16 – LEN[7:0] Transaction Length

These bits define the transaction length of a DMA and/or 32-bit transaction from 0-255 bytes. The Transfer Length Enable (LENEN) bit must be written to ‘1’ to use DMA.

Bit 15 – TENBITEN Ten Bit Addressing Enable

This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit address transmission.

ValueDescription
010-bit addressing disabled.
110-bit addressing enabled.

Bit 13 – LENEN Transfer Length Enable

ValueDescription
0Automatic transfer length disabled.
1Automatic transfer length enabled.

Bits 10:0 – ADDR[10:0] Address

When ADDR is written, the consecutive operation depends on the Bus state:

Table 34-6. 
StateDescription
UNKNOWNINTFLAG.MB and STATUS.BUSERR are set and the operation is terminated.
BUSYThe I2C host awaits further operation until the bus becomes IDLE.
IDLEThe I2C host issues a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low and STATUS.CLKHOLD and INTFLAG.MB are set.
OWNERA repeated start sequence is performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set.
Note: STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB is cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the host logic to perform any bus protocol related operations.

The I2C host control logic uses bit ‘0’ of ADDR as the bus protocol’s read/write flag (R/W); ‘0’ for write and ‘1’ for read.