34.10.8 Status
| Name: | STATUS |
| Offset: | 0x1A |
| Reset: | 0x0000 |
| Property: | Write-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LENERR | SEXTTOUT | MEXTTOUT | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKHOLD | LOWTOUT | BUSSTATE[1:0] | RXNACK | ARBLOST | BUSERR | ||||
| Access | R | R/W | R/W | R/W | R | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 10 – LENERR Transaction Length Error
This bit is set when automatic length is used for a DMA and/or 32-bit transaction and the client sends a NACK before ADDR.LEN bytes are written by the host.
Writing ‘1’ to this bit location clears STATUS.LENERR. This flag is automatically cleared when writing to the ADDR register.
Writing ‘0’ to this bit has no effect.
This bit is not write-synchronized.
Bit 9 – SEXTTOUT Client SCL Low Extend Time-Out
This bit is set if a client SCL low extend time-out occurs.
This bit is automatically cleared when writing to the ADDR register.
Writing ‘1’ to this bit location clears SEXTTOUT. Normal use of the I2C interface does not require the SEXTTOUT flag to be cleared by this method.
Writing ‘0’ to this bit has no effect.
This bit is not write-synchronized.
Bit 8 – MEXTTOUT Host SCL Low Extend Time-Out
This bit is set if a Host SCL low time-out occurs.
Writing ‘1’ to this bit location clears STATUS.MEXTTOUT. This flag is automatically cleared when writing to the ADDR register.
Writing ‘0’ to this bit has no effect.
This bit is not write-synchronized.
Bit 7 – CLKHOLD Clock Hold
This bit is set when the host is holding the SCL line low, stretching the I2C clock. Software must consider this bit when INTFLAG.SB or INTFLAG.MB is set.
This bit is cleared when the corresponding Interrupt flag is cleared and the next operation is given.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit has no effect.
This bit is not write-synchronized.
Bit 6 – LOWTOUT SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing ‘1’ to this bit location clears this bit. This flag is automatically cleared when writing to the ADDR register.
Writing ‘0’ to this bit has no effect.
This bit is not write-synchronized.
Bits 5:4 – BUSSTATE[1:0] Bus State
These bits indicate the current I2C Bus state.
When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the Idle state. The Bus state cannot be forced into any other state.
Writing BUSSTATE to Idle sets SYNCBUSY.SYSOP.
| Value | Name | Description |
|---|---|---|
| 0x0 | UNKNOWN | The Bus state is unknown to the I2C host and waits for a Stop condition to be detected or wait to be forced into an Idle state by software |
| 0x1 | IDLE | The Bus state is waiting for a transaction to be initialized |
| 0x2 | OWNER | The I2C host is the current owner of the bus |
| 0x3 | BUSY | Some other I2C host owns the bus |
Bit 2 – RXNACK Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit has no effect.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Client responded with ACK. |
| 1 | Client responded with NACK. |
Bit 1 – ARBLOST Arbitration Lost
This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit or while issuing a Start or Repeated Start condition on the bus. The Host on Bus Interrupt flag (INTFLAG.MB) is set when STATUS.ARBLOST is set.
Writing the ADDR.ADDR register automatically clears STATUS.ARBLOST.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
This bit is not write-synchronized.
Bit 0 – BUSERR Bus Error
This bit indicates that an illegal Bus condition occurred on the bus, regardless of bus ownership. An illegal Bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A Start condition directly followed by a Stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and sets BUSERR.
If the I2C host is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB are set in addition to BUSERR.
Writing the ADDR.ADDR register automatically clears the BUSERR flag.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
This bit is not write-synchronized.