34.10.1 Control A

This bit enables the SCL low time-out. If SCL is held low for 25-35 ms, the host releases its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted.

INTFLAG.SB or INTFLAG.MB is set as normal but the clock hold is released. The STATUS.LOWTOUT and STATUS.BUSERR status bits is set.

This bit is not synchronized.

If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic is set to Idle. An inactive bus arises when either an I²C host or client is holding the SCL low.

Enabling this option is necessary for SMBus compatibility but can also be used in a non-SMBus setup.

Calculated time-out periods are based on a 100 kHz baud rate.

These bits are not synchronized.

This bit controls when SCL is stretched for software interaction.

This bit is not synchronized.

These bits define bus speed.

These bits are not synchronized.

This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25 ms from the initial START to a STOP, the host releases its clock hold, if enabled, and completes the current transaction. A STOP will automatically be transmitted.

SB or MB is set as normal but CLKHOLD is release. The MEXTTOUT and BUSERR status bits is set.

This bit is not synchronized.

This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10 ms from START-to-ACK, ACK-to-ACK or ACK-to-STOP the host releases its clock hold if enabled and completes the current transaction. A STOP will automatically be transmitted.

SB or MB is set as normal but CLKHOLD is released. The MEXTTOUT and BUSERR status bits is set.

This bit is not synchronized.

This bit sets the pin usage to either two- or four-wire operation:

This bit is not synchronized.

This bit defines the functionality in the Standby Sleep mode.

This bit is not synchronized.

These bits must be written to 0x5 to select the I²C host serial communication interface of the SERCOM.

These bits are not synchronized.

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE reads back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) is set. SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state and the SERCOM is disabled.

Writing ‘1’ to CTRLA.SWRST always takes precedence, meaning that all other writes in the same write operation is discarded. Any register write access during the ongoing Reset results in an APB error. Reading any register returns the Reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.