34.10.7 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x18 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | RXFF | TXFE | SB | MB | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error
This flag is cleared by writing ‘1’ to it.
This bit is set when any error is detected. Errors that set this flag have corresponding status bits in the STATUS register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST and BUSERR.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the flag.
Bit 4 – RXFF RX FIFO Full
This flag is set when RX FIFO Threshold locations are fulfilled.
The flag is cleared when the RX FIFO is empty.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the RX FIFO Full interrupt flag.
Bit 3 – TXFE TX FIFO Empty
This flag is set when TX FIFO Threshold locations are available.
The flag is cleared when the TX FIFO is full.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the TX FIFO Empty Interrupt flag.
Bit 1 – SB Client on Bus
The Client on Bus flag (SB) is set when a byte is successfully received in the Host Read mode, for example, no arbitration lost or bus error occurred during the operation. When this flag is set, the host forces the SCL line low, stretching the I2C clock period. The SCL line is released and SB is cleared on one of the following actions:
- Writing to ADDR.ADDR
- Writing to DATA.DATA
- Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN)
- Writing a valid command to CTRLB.CMD
Writing ‘1’ to this bit location clears the SB flag. The transaction will not continue or be terminated until one of the above actions is performed.
Writing ‘0’ to this bit has no effect.
Bit 0 – MB Host on Bus
This flag is set when a byte is transmitted in Host Write mode. The flag is set regardless of the occurrence of a bus error or an Arbitration Lost condition. MB is also set when arbitration is lost during sending of a NACK in the Host Read mode or when issuing a Start condition if the bus state is unknown. When this flag is set and arbitration is not lost, the host forces the SCL line low, stretching the I2C clock period. The SCL line is released and MB is cleared on one of the following actions:
- Writing to ADDR.ADDR
- Writing to DATA.DATA
- Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN)
- Writing a valid command to CTRLB.CMD
Writing ‘1’ to this bit location clears the MB flag. The transaction will not continue or be terminated until one of the above actions is performed.
Writing ‘0’ to this bit has no effect.